#include <stdio.h>
#include <stdlib.h>

#include <assert.h>

#include "basics.h"
#include "fatal.h"
#include "allocate.h"
#include "simcore.h"
#include "config.h"
#include "xicache.h"
#include "xdcache.h"
#include "tsparcv9.h"
#include "tsparcv9internal.h"
#include "sparcv9regs.h"
#include "sparcv9cc.h"
#include "magictraps.h"
#include "hostnative.h"
#include "sparcv9decode.h"

	/*
	 * Implementation(s) of pre-decoded sparcv9 specific instructions.
	 */

#define	IMPL( _n )	void decoded_impl_sparcv9_##_n (simcpu_t *sp, xicache_instn_t * xcip) {
#define	ENDI		NEXT_INSTN(sp); ENDDEF
#define	ENDDEF		}

/* this functions are defined in sparcv9 decode
#define SET_OP(_n)      do { exec_funcp = decoded_impl_##_n ; } while (0)
#define SET_OPv9(_n)    do { exec_funcp = decoded_impl_sparcv9_##_n ; } while (0)
*/

#define	_U	(1 << V9_fcc_u)
#define	_G	(1 << V9_fcc_g)
#define	_L	(1 << V9_fcc_l)
#define	_E	(1 << V9_fcc_e)

static uint8_t sparcv9_fcc_magic[16] = {
	0,		/* never */
	_U|_G|_L,	/* NE */
	_G|_L,		/* LG */
	_U|_L,		/* UL */
	_L,		/* L */
	_U|_G,		/* UG */
	_G,		/* G */
	_U,		/* U */
	_U|_G|_L|_E,	/* always */
	_E,		/* E */
	_U|_E,		/* UE */
	_G|_E,		/* GE */
	_U|_G|_E,	/* UGE */
	_L|_E,		/* LE */
	_U|_L|_E,	/* ULE */
	_G|_L|_E	/* O */
};

#undef	_U
#undef	_G
#undef	_L
#undef	_E

/* ------------------------------------------------------------ */

	/*
	 * Instruction: sparcv9_add_co_imm
	 */

#if !defined(HAS_NATIVE_sparcv9_add_co_imm)	/* { */

IMPL(add_co_imm)
	int64_t s1 = Rsrc1;
	int64_t s2 = Simm16;
	int64_t d;
	uint64_t v, c;

	d = s1 + s2;

	v = (s1 & s2 & ~d) | (~s1 & ~s2 & d);
	c = (s1 & s2) | (~d & (s1 | s2));

	sp->v9_ccr  = V9_xcc_v((v >> 63) & 1);
	sp->v9_ccr |= V9_icc_v((v >> 31) & 1);
	sp->v9_ccr |= V9_xcc_c((c >> 63) & 1);
	sp->v9_ccr |= V9_icc_c((c >> 31) & 1);
	sp->v9_ccr |= V9_xcc_n((d >> 63) & 1);
	sp->v9_ccr |= V9_icc_n((d >> 31) & 1);
	sp->v9_ccr |= V9_xcc_z(d ? 0 : 1);
	sp->v9_ccr |= V9_icc_z((d & MASK64(31,0)) ? 0 : 1);
	Rdest = d;
	ENDI

#endif	/* } */


	/*
	 * Instruction: sparcv9_add_co_rrr
	 */

#if !defined(HAS_NATIVE_sparcv9_add_co_rrr)	/* { */

IMPL(add_co_rrr)
	uint64_t s1 = Rsrc1, s2 = Rsrc2, d;
	uint64_t v, c;

	d = Rsrc1 + Rsrc2;

	v = (s1 & s2 & ~d) | (~s1 & ~s2 & d);
	c = (s1 & s2) | (~d & (s1 | s2));

	sp->v9_ccr  = V9_xcc_v((v >> 63) & 1);
	sp->v9_ccr |= V9_icc_v((v >> 31) & 1);
	sp->v9_ccr |= V9_xcc_c((c >> 63) & 1);
	sp->v9_ccr |= V9_icc_c((c >> 31) & 1);
	sp->v9_ccr |= V9_xcc_n((d >> 63) & 1);
	sp->v9_ccr |= V9_icc_n((d >> 31) & 1);
	sp->v9_ccr |= V9_xcc_z(d ? 0 : 1);
	sp->v9_ccr |= V9_icc_z((d & MASK64(31,0)) ? 0 : 1);
	Rdest = d;
	ENDI

#endif	/* } */


	/*
	 * Instruction: sparcv9_add_co_imm_rd0
	 */

#if !defined(HAS_NATIVE_sparcv9_add_co_imm_rd0)	/* { */

IMPL(add_co_imm_rd0)
	int64_t s1 = Rsrc1, s2 = (int64_t)(int32_t)Simm16, d;
	uint64_t v, c;

	d = s1 + s2;

	v = (s1 & s2 & ~d) | (~s1 & ~s2 & d);
	c = (s1 & s2) | (~d & (s1 | s2));

	sp->v9_ccr  = V9_xcc_v((v >> 63) & 1);
	sp->v9_ccr |= V9_icc_v((v >> 31) & 1);
	sp->v9_ccr |= V9_xcc_c((c >> 63) & 1);
	sp->v9_ccr |= V9_icc_c((c >> 31) & 1);
	sp->v9_ccr |= V9_xcc_n((d >> 63) & 1);
	sp->v9_ccr |= V9_icc_n((d >> 31) & 1);
	sp->v9_ccr |= V9_xcc_z(d ? 0 : 1);
	sp->v9_ccr |= V9_icc_z((d & MASK64(31,0)) ? 0 : 1);
	ENDI

#endif	/* } */





	/*
	 * Instruction: sparcv9_add_co_rrr_rd0
	 */

#if !defined(HAS_NATIVE_sparcv9_add_co_rrr_rd0)	/* { */

IMPL(add_co_rrr_rd0)
	int64_t s1 = Rsrc1, s2 = Rsrc2, d;
	uint64_t v, c;

	d = s1 + s2;

	v = (s1 & s2 & ~d) | (~s1 & ~s2 & d);
	c = (s1 & s2) | (~d & (s1 | s2));

	sp->v9_ccr  = V9_xcc_v((v >> 63) & 1);
	sp->v9_ccr |= V9_icc_v((v >> 31) & 1);
	sp->v9_ccr |= V9_xcc_c((c >> 63) & 1);
	sp->v9_ccr |= V9_icc_c((c >> 31) & 1);
	sp->v9_ccr |= V9_xcc_n((d >> 63) & 1);
	sp->v9_ccr |= V9_icc_n((d >> 31) & 1);
	sp->v9_ccr |= V9_xcc_z(d ? 0 : 1);
	sp->v9_ccr |= V9_icc_z((d & MASK64(31,0)) ? 0 : 1);
	ENDI

#endif	/* } */





	/*
	 * Instruction: sparcv9_add_ci_imm
	 */

#if !defined(HAS_NATIVE_sparcv9_add_ci_imm)	/* { */

IMPL(add_ci_imm)
	int64_t s1 = Rsrc1, s2 = (int64_t)(int32_t)Simm16, d;

	d = s1 + s2 + (sp->v9_ccr & 1);
	Rdest = d;
	ENDI

#endif	/* } */


	/*
	 * Instruction: sparcv9_add_ci_rrr
	 */

#if !defined(HAS_NATIVE_sparcv9_add_ci_rrr)	/* { */

IMPL(add_ci_rrr)
	int64_t s1 = Rsrc1, s2 = Rsrc2, d;

	d = s1 + s2 + (sp->v9_ccr & 1);
	Rdest = d;
	ENDI

#endif	/* } */


	/*
	 * Instruction: sparcv9_add_cico_imm
	 */

#if !defined(HAS_NATIVE_sparcv9_add_cico_imm)	/* { */

IMPL(add_cico_imm)
	int64_t s1 = Rsrc1, s2 = (int64_t)(int32_t)Simm16, d;
	uint64_t v, c;

	d = s1 + s2 + (sp->v9_ccr & 1);

	v = (s1 & s2 & ~d) | (~s1 & ~s2 & d);
	c = (s1 & s2) | (~d & (s1 | s2));

	sp->v9_ccr  = V9_xcc_v((v >> 63) & 1);
	sp->v9_ccr |= V9_icc_v((v >> 31) & 1);
	sp->v9_ccr |= V9_xcc_c((c >> 63) & 1);
	sp->v9_ccr |= V9_icc_c((c >> 31) & 1);
	sp->v9_ccr |= V9_xcc_n((d >> 63) & 1);
	sp->v9_ccr |= V9_icc_n((d >> 31) & 1);
	sp->v9_ccr |= V9_xcc_z(d ? 0 : 1);
	sp->v9_ccr |= V9_icc_z((d & MASK64(31,0)) ? 0 : 1);
	Rdest = d;
	ENDI

#endif	/* } */





	/*
	 * Instruction: sparcv9_add_cico_rrr
	 */

#if !defined(HAS_NATIVE_sparcv9_add_cico_rrr)	/* { */

IMPL(add_cico_rrr)
	int64_t s1 = Rsrc1, s2 = Rsrc2, d;
	uint64_t v, c;

	d = s1 + s2 + (sp->v9_ccr & 1);

	v = (s1 & s2 & ~d) | (~s1 & ~s2 & d);
	c = (s1 & s2) | (~d & (s1 | s2));

	sp->v9_ccr  = V9_xcc_v((v >> 63) & 1);
	sp->v9_ccr |= V9_icc_v((v >> 31) & 1);
	sp->v9_ccr |= V9_xcc_c((c >> 63) & 1);
	sp->v9_ccr |= V9_icc_c((c >> 31) & 1);
	sp->v9_ccr |= V9_xcc_n((d >> 63) & 1);
	sp->v9_ccr |= V9_icc_n((d >> 31) & 1);
	sp->v9_ccr |= V9_xcc_z(d ? 0 : 1);
	sp->v9_ccr |= V9_icc_z((d & MASK64(31,0)) ? 0 : 1);
	Rdest = d;
	ENDI

#endif	/* } */





	/*
	 * Instruction: sparcv9_add_cico_imm_rd0
	 */

#if !defined(HAS_NATIVE_sparcv9_add_cico_imm_rd0)	/* { */

IMPL(add_cico_imm_rd0)
	int64_t s1 = Rsrc1, s2 = (int64_t)(int32_t)Simm16, d;
	uint64_t v, c;

	d = s1 + s2 + (sp->v9_ccr & 1);

	v = (s1 & s2 & ~d) | (~s1 & ~s2 & d);
	c = (s1 & s2) | (~d & (s1 | s2));

	sp->v9_ccr  = V9_xcc_v((v >> 63) & 1);
	sp->v9_ccr |= V9_icc_v((v >> 31) & 1);
	sp->v9_ccr |= V9_xcc_c((c >> 63) & 1);
	sp->v9_ccr |= V9_icc_c((c >> 31) & 1);
	sp->v9_ccr |= V9_xcc_n((d >> 63) & 1);
	sp->v9_ccr |= V9_icc_n((d >> 31) & 1);
	sp->v9_ccr |= V9_xcc_z(d ? 0 : 1);
	sp->v9_ccr |= V9_icc_z((d & MASK64(31,0)) ? 0 : 1);
	ENDI

#endif	/* } */


	/*
	 * Instruction: sparcv9_add_cico_rrr_rd0
	 */

#if !defined(HAS_NATIVE_sparcv9_add_cico_rrr_rd0)	/* { */

IMPL(add_cico_rrr_rd0)
	int64_t s1 = Rsrc1, s2 = Rsrc2, d;
	uint64_t v, c;

	d = s1 + s2 + (sp->v9_ccr & 1);

	v = (s1 & s2 & ~d) | (~s1 & ~s2 & d);
	c = (s1 & s2) | (~d & (s1 | s2));

	sp->v9_ccr  = V9_xcc_v((v >> 63) & 1);
	sp->v9_ccr |= V9_icc_v((v >> 31) & 1);
	sp->v9_ccr |= V9_xcc_c((c >> 63) & 1);
	sp->v9_ccr |= V9_icc_c((c >> 31) & 1);
	sp->v9_ccr |= V9_xcc_n((d >> 63) & 1);
	sp->v9_ccr |= V9_icc_n((d >> 31) & 1);
	sp->v9_ccr |= V9_xcc_z(d ? 0 : 1);
	sp->v9_ccr |= V9_icc_z((d & MASK64(31,0)) ? 0 : 1);

	ENDI

#endif	/* } */





	/*
	 * Instruction: sparcv9_sub_co_imm
	 */

#if !defined(HAS_NATIVE_sparcv9_sub_co_imm)	/* { */

IMPL(sub_co_imm)
	int64_t s1 = Rsrc1;
	int64_t s2 = Simm16;
	int64_t d;
	uint64_t v, c;

	d = s1 - s2;

	v = (s1 & ~s2 & ~d) | (~s1 & s2 & d);
	c = (~s1 & s2) | (d & (~s1 | s2));

	sp->v9_ccr  = V9_xcc_v((v >> 63) & 1);
	sp->v9_ccr |= V9_icc_v((v >> 31) & 1);
	sp->v9_ccr |= V9_xcc_c((c >> 63) & 1);
	sp->v9_ccr |= V9_icc_c((c >> 31) & 1);
	sp->v9_ccr |= V9_xcc_n((d >> 63) & 1);
	sp->v9_ccr |= V9_icc_n((d >> 31) & 1);
	sp->v9_ccr |= V9_xcc_z(d ? 0 : 1);
	sp->v9_ccr |= V9_icc_z((d & MASK64(31,0)) ? 0 : 1);
	Rdest = d;
	ENDI

#endif	/* } */





	/*
	 * Instruction: sparcv9_sub_co_rrr
	 */

#if !defined(HAS_NATIVE_sparcv9_sub_co_rrr)	/* { */

IMPL(sub_co_rrr)
	int64_t s1 = Rsrc1;
	int64_t s2 = Rsrc2;
	int64_t d;
	uint64_t v, c;

	d = s1 - s2;

	v = (s1 & ~s2 & ~d) | (~s1 & s2 & d);
	c = (~s1 & s2) | (d & (~s1 | s2));

	sp->v9_ccr  = V9_xcc_v((v >> 63) & 1);
	sp->v9_ccr |= V9_icc_v((v >> 31) & 1);
	sp->v9_ccr |= V9_xcc_c((c >> 63) & 1);
	sp->v9_ccr |= V9_icc_c((c >> 31) & 1);
	sp->v9_ccr |= V9_xcc_n((d >> 63) & 1);
	sp->v9_ccr |= V9_icc_n((d >> 31) & 1);
	sp->v9_ccr |= V9_xcc_z(d ? 0 : 1);
	sp->v9_ccr |= V9_icc_z((d & MASK64(31,0)) ? 0 : 1);
	Rdest = d;
	ENDI

#endif	/* } */





	/*
	 * Instruction: sparcv9_sub_co_imm_rd0
	 */

#if !defined(HAS_NATIVE_sparcv9_sub_co_imm_rd0)	/* { */

IMPL(sub_co_imm_rd0)
	int64_t s1 = Rsrc1;
	int64_t s2 = Simm16;
	int64_t d;
	uint64_t v, c;

	d = s1 - s2;

	v = (s1 & ~s2 & ~d) | (~s1 & s2 & d);
	c = (~s1 & s2) | (d & (~s1 | s2));

	sp->v9_ccr  = V9_xcc_v((v >> 63) & 1);
	sp->v9_ccr |= V9_icc_v((v >> 31) & 1);
	sp->v9_ccr |= V9_xcc_c((c >> 63) & 1);
	sp->v9_ccr |= V9_icc_c((c >> 31) & 1);
	sp->v9_ccr |= V9_xcc_n((d >> 63) & 1);
	sp->v9_ccr |= V9_icc_n((d >> 31) & 1);
	sp->v9_ccr |= V9_xcc_z(d ? 0 : 1);
	sp->v9_ccr |= V9_icc_z((d & MASK64(31,0)) ? 0 : 1);
	ENDI

#endif	/* } */





	/*
	 * Instruction: sparcv9_sub_co_rrr_rd0
	 */

#if !defined(HAS_NATIVE_sparcv9_sub_co_rrr_rd0)	/* { */

IMPL(sub_co_rrr_rd0)
	int64_t s1 = Rsrc1;
	int64_t s2 = Rsrc2;
	int64_t d;
	uint64_t v, c;

	d = s1 - s2;

	v = (s1 & ~s2 & ~d) | (~s1 & s2 & d);
	c = (~s1 & s2) | (d & (~s1 | s2));

	sp->v9_ccr  = V9_xcc_v((v >> 63) & 1);
	sp->v9_ccr |= V9_icc_v((v >> 31) & 1);
	sp->v9_ccr |= V9_xcc_c((c >> 63) & 1);
	sp->v9_ccr |= V9_icc_c((c >> 31) & 1);
	sp->v9_ccr |= V9_xcc_n((d >> 63) & 1);
	sp->v9_ccr |= V9_icc_n((d >> 31) & 1);
	sp->v9_ccr |= V9_xcc_z(d ? 0 : 1);
	sp->v9_ccr |= V9_icc_z((d & MASK64(31,0)) ? 0 : 1);
	ENDI

#endif	/* } */





	/*
	 * Instruction: sparcv9_sub_ci_imm
	 */

#if !defined(HAS_NATIVE_sparcv9_sub_ci_imm)	/* { */

IMPL(sub_ci_imm)
	int64_t s1 = Rsrc1, s2 = (int64_t)(int32_t)Simm16, d;

	d = s1 - s2 - (sp->v9_ccr & 1);
	Rdest = d;
	ENDI

#endif	/* } */





	/*
	 * Instruction: sparcv9_sub_ci_rrr
	 */

#if !defined(HAS_NATIVE_sparcv9_sub_ci_rrr)	/* { */

IMPL(sub_ci_rrr)
	int64_t s1 = Rsrc1, s2 = Rsrc2, d;

	d = s1 - s2 - (sp->v9_ccr & 1);
	Rdest = d;
	ENDI

#endif	/* } */



	/*
	 * Instruction: sparcv9_sub_cico_imm
	 */

#if !defined(HAS_NATIVE_sparcv9_sub_cico_imm)	/* { */

IMPL(sub_cico_imm)
	int64_t s1 = Rsrc1, s2 = (int64_t)(int32_t)Simm16, d;
	uint64_t v, c;

	d = s1 - s2 - (sp->v9_ccr & 1);

	v = (s1 & ~s2 & ~d) | (~s1 & s2 & d);
	c = (~s1 & s2) | (d & (~s1 | s2));

	sp->v9_ccr  = V9_xcc_v((v >> 63) & 1);
	sp->v9_ccr |= V9_icc_v((v >> 31) & 1);
	sp->v9_ccr |= V9_xcc_c((c >> 63) & 1);
	sp->v9_ccr |= V9_icc_c((c >> 31) & 1);
	sp->v9_ccr |= V9_xcc_n((d >> 63) & 1);
	sp->v9_ccr |= V9_icc_n((d >> 31) & 1);
	sp->v9_ccr |= V9_xcc_z(d ? 0 : 1);
	sp->v9_ccr |= V9_icc_z((d & MASK64(31,0)) ? 0 : 1);
	Rdest = d;
	ENDI

#endif	/* } */


	/*
	 * Instruction: sparcv9_sub_cico_rrr
	 */

#if !defined(HAS_NATIVE_sparcv9_sub_cico_rrr)	/* { */

IMPL(sub_cico_rrr)
	int64_t s1 = Rsrc1, s2 = Rsrc2, d;
	uint64_t v, c;

	d = s1 - s2 - (sp->v9_ccr & 1);

	v = (s1 & ~s2 & ~d) | (~s1 & s2 & d);
	c = (~s1 & s2) | (d & (~s1 | s2));

	sp->v9_ccr  = V9_xcc_v((v >> 63) & 1);
	sp->v9_ccr |= V9_icc_v((v >> 31) & 1);
	sp->v9_ccr |= V9_xcc_c((c >> 63) & 1);
	sp->v9_ccr |= V9_icc_c((c >> 31) & 1);
	sp->v9_ccr |= V9_xcc_n((d >> 63) & 1);
	sp->v9_ccr |= V9_icc_n((d >> 31) & 1);
	sp->v9_ccr |= V9_xcc_z(d ? 0 : 1);
	sp->v9_ccr |= V9_icc_z((d & MASK64(31,0)) ? 0 : 1);
	Rdest = d;
	ENDI

#endif	/* } */



	/*
	 * Instruction: sparcv9_sub_cico_imm_rd0
	 */

#if !defined(HAS_NATIVE_sparcv9_sub_cico_imm_rd0)	/* { */

IMPL(sub_cico_imm_rd0)
	int64_t s1 = Rsrc1, s2 = (int64_t)(int32_t)Simm16, d;
	uint64_t v, c;

	d = s1 - s2 - (sp->v9_ccr & 1);

	v = (s1 & ~s2 & ~d) | (~s1 & s2 & d);
	c = (~s1 & s2) | (d & (~s1 | s2));

	sp->v9_ccr  = V9_xcc_v((v >> 63) & 1);
	sp->v9_ccr |= V9_icc_v((v >> 31) & 1);
	sp->v9_ccr |= V9_xcc_c((c >> 63) & 1);
	sp->v9_ccr |= V9_icc_c((c >> 31) & 1);
	sp->v9_ccr |= V9_xcc_n((d >> 63) & 1);
	sp->v9_ccr |= V9_icc_n((d >> 31) & 1);
	sp->v9_ccr |= V9_xcc_z(d ? 0 : 1);
	sp->v9_ccr |= V9_icc_z((d & MASK64(31,0)) ? 0 : 1);
	ENDI

#endif	/* } */





	/*
	 * Instruction: sparcv9_sub_cico_rrr_rd0
	 */

#if !defined(HAS_NATIVE_sparcv9_sub_cico_rrr_rd0)	/* { */

IMPL(sub_cico_rrr_rd0)
	int64_t s1 = Rsrc1, s2 = Rsrc2, d;
	uint64_t v, c;

	d = s1 - s2 - (sp->v9_ccr & 1);

	v = (s1 & ~s2 & ~d) | (~s1 & s2 & d);
	c = (~s1 & s2) | (d & (~s1 | s2));

	sp->v9_ccr  = V9_xcc_v((v >> 63) & 1);
	sp->v9_ccr |= V9_icc_v((v >> 31) & 1);
	sp->v9_ccr |= V9_xcc_c((c >> 63) & 1);
	sp->v9_ccr |= V9_icc_c((c >> 31) & 1);
	sp->v9_ccr |= V9_xcc_n((d >> 63) & 1);
	sp->v9_ccr |= V9_icc_n((d >> 31) & 1);
	sp->v9_ccr |= V9_xcc_z(d ? 0 : 1);
	sp->v9_ccr |= V9_icc_z((d & MASK64(31,0)) ? 0 : 1);
	ENDI

#endif	/* } */



#define	LOGIC_OP(_res, _op)	do {				\
		uint64_t result;				\
		result = _op;					\
		sp->v9_ccr = V9_xcc_n((result>>63)&1)		\
			| V9_xcc_z(result==0LL)			\
			| V9_icc_n((result>>31)&1)		\
			| V9_icc_z((result&MASK64(31,0))==0LL);	\
		_res;						\
	} while (0)



	/*
	 * Instruction: sparcv9_and_cc_imm
	 */

#if !defined(HAS_NATIVE_sparcv9_and_cc_imm)	/* { */

IMPL(and_cc_imm)
	LOGIC_OP(Rdest = result, Rsrc1 & Simm16);
	ENDI

#endif	/* } */





	/*
	 * Instruction: sparcv9_and_cc_rrr
	 */

#if !defined(HAS_NATIVE_sparcv9_and_cc_rrr)	/* { */

IMPL(and_cc_rrr)
	LOGIC_OP(Rdest = result, Rsrc1 & Rsrc2);
	ENDI

#endif	/* } */





	/*
	 * Instruction: sparcv9_and_cc_imm_rd0
	 */

#if !defined(HAS_NATIVE_sparcv9_and_cc_imm_rd0)	/* { */

IMPL(and_cc_imm_rd0)
	LOGIC_OP(/*nada*/, Rsrc1 & Simm16);
	ENDI

#endif	/* } */





	/*
	 * Instruction: sparcv9_and_cc_rrr_rd0
	 */

#if !defined(HAS_NATIVE_sparcv9_and_cc_rrr_rd0)	/* { */

IMPL(and_cc_rrr_rd0)
	LOGIC_OP(/*nada*/, Rsrc1 & Rsrc2);
	ENDI

#endif	/* } */





	/*
	 * Instruction: sparcv9_andn_cc_rrr
	 */

#if !defined(HAS_NATIVE_sparcv9_andn_cc_rrr)	/* { */

IMPL(andn_cc_rrr)
	LOGIC_OP(Rdest=result, ~(Rsrc1 & Rsrc2) );
	ENDI

#endif	/* } */





	/*
	 * Instruction: sparcv9_andn_cc_rrr_rd0
	 */

#if !defined(HAS_NATIVE_sparcv9_andn_cc_rrr_rd0)	/* { */

IMPL(andn_cc_rrr_rd0)
	LOGIC_OP(/*nada*/, ~(Rsrc1 & Rsrc2) );
	ENDI

#endif	/* } */





	/*
	 * Instruction: sparcv9_or_cc_imm
	 */

#if !defined(HAS_NATIVE_sparcv9_or_cc_imm)	/* { */

IMPL(or_cc_imm)
	LOGIC_OP(Rdest=result, Rsrc1 | Simm16 );
	ENDI

#endif	/* } */





	/*
	 * Instruction: sparcv9_or_cc_rrr
	 */

#if !defined(HAS_NATIVE_sparcv9_or_cc_rrr)	/* { */

IMPL(or_cc_rrr)
	LOGIC_OP(Rdest=result, Rsrc1 | Rsrc2 );
	ENDI

#endif	/* } */





	/*
	 * Instruction: sparcv9_or_cc_imm_rd0
	 */

#if !defined(HAS_NATIVE_sparcv9_or_cc_imm_rd0)	/* { */

IMPL(or_cc_imm_rd0)
	LOGIC_OP(/*nada*/, Rsrc1 | Simm16 );
	ENDI

#endif	/* } */





	/*
	 * Instruction: sparcv9_or_cc_rrr_rd0
	 */

#if !defined(HAS_NATIVE_sparcv9_or_cc_rrr_rd0)	/* { */

IMPL(or_cc_rrr_rd0)
	LOGIC_OP(/*nada*/, Rsrc1 | Rsrc2 );
	ENDI

#endif	/* } */





	/*
	 * Instruction: sparcv9_orn_cc_rrr
	 */

#if !defined(HAS_NATIVE_sparcv9_orn_cc_rrr)	/* { */

IMPL(orn_cc_rrr)
	LOGIC_OP(Rdest=result, ~(Rsrc1 | Rsrc2) );
	ENDI

#endif	/* } */





	/*
	 * Instruction: sparcv9_orn_cc_rrr_rd0
	 */

#if !defined(HAS_NATIVE_sparcv9_orn_cc_rrr_rd0)	/* { */

IMPL(orn_cc_rrr_rd0)
	LOGIC_OP(/*nada*/, ~(Rsrc1 | Rsrc2) );
	ENDI

#endif	/* } */





	/*
	 * Instruction: sparcv9_xor_cc_imm
	 */

#if !defined(HAS_NATIVE_sparcv9_xor_cc_imm)	/* { */

IMPL(xor_cc_imm)
	LOGIC_OP(Rdest=result, Rsrc1 ^ Simm16 );
	ENDI

#endif	/* } */





	/*
	 * Instruction: sparcv9_xor_cc_rrr
	 */

#if !defined(HAS_NATIVE_sparcv9_xor_cc_rrr)	/* { */

IMPL(xor_cc_rrr)
	LOGIC_OP(Rdest=result, Rsrc1 ^ Rsrc2 );
	ENDI

#endif	/* } */





	/*
	 * Instruction: sparcv9_xor_cc_imm_rd0
	 */

#if !defined(HAS_NATIVE_sparcv9_xor_cc_imm_rd0)	/* { */

IMPL(xor_cc_imm_rd0)
	LOGIC_OP(/*nada*/, Rsrc1 ^ Simm16 );
	ENDI

#endif	/* } */





	/*
	 * Instruction: sparcv9_xor_cc_rrr_rd0
	 */

#if !defined(HAS_NATIVE_sparcv9_xor_cc_rrr_rd0)	/* { */

IMPL(xor_cc_rrr_rd0)
	LOGIC_OP(/*nada*/, Rsrc1 ^ Rsrc2 );
	ENDI

#endif	/* } */





	/*
	 * Instruction: sparcv9_xnor_cc_rrr
	 */

#if !defined(HAS_NATIVE_sparcv9_xnor_cc_rrr)	/* { */

IMPL(xnor_cc_rrr)
	LOGIC_OP(Rdest=result, ~(Rsrc1 ^ Rsrc2) );
	ENDI

#endif	/* } */





	/*
	 * Instruction: sparcv9_xnor_cc_rrr_rd0
	 */

#if !defined(HAS_NATIVE_sparcv9_xnor_cc_rrr_rd0)	/* { */

IMPL(xnor_cc_rrr_rd0)
	LOGIC_OP(/*nada*/, ~(Rsrc1 ^ Rsrc2) );
	ENDI

#endif	/* } */





	/*
	 * Instruction: sparcv9_bne_icc
	 */

#if !defined(HAS_NATIVE_sparcv9_bne_icc)	/* { */

IMPL(bne_icc)
	if (!(sp->v9_ccr & V9_icc_z_mask)) {
		tvaddr_t tpc = Rpc + SBRoffset32;
		Rpc = Rnpc;
		Rnpc = tpc;
		return;
	}
	ENDI

#endif	/* } */





	/*
	 * Instruction: sparcv9_be_icc
	 */

#if !defined(HAS_NATIVE_sparcv9_be_icc)	/* { */

IMPL(be_icc)
	if (sp->v9_ccr & V9_icc_z_mask) {
		tvaddr_t tpc = Rpc + SBRoffset32;
		Rpc = Rnpc;
		Rnpc = tpc;
		return;
	}
	ENDI

#endif	/* } */





	/*
	 * Instruction: sparcv9_bg_icc
	 */

#if !defined(HAS_NATIVE_sparcv9_bg_icc)	/* { */

IMPL(bg_icc)
	int cc = V9_ext_icc(sp->v9_ccr);
	if ( (sparcv9_cc_magic[cond_g] >> cc) &1 ) {
		tvaddr_t tpc = Rpc + SBRoffset32;
		Rpc = Rnpc;
		Rnpc = tpc;
		return;
	}
	ENDI

#endif	/* } */





	/*
	 * Instruction: sparcv9_ble_icc
	 */

#if !defined(HAS_NATIVE_sparcv9_ble_icc)	/* { */

IMPL(ble_icc)
	int cc = V9_ext_icc(sp->v9_ccr);
	if ( (sparcv9_cc_magic[cond_le] >> cc) &1 ) {
		tvaddr_t tpc = Rpc + SBRoffset32;
		Rpc = Rnpc;
		Rnpc = tpc;
		return;
	}
	ENDI

#endif	/* } */





	/*
	 * Instruction: sparcv9_bge_icc
	 */

#if !defined(HAS_NATIVE_sparcv9_bge_icc)	/* { */

IMPL(bge_icc)
	int cc = V9_ext_icc(sp->v9_ccr);
	if ( (sparcv9_cc_magic[cond_ge] >> cc) &1 ) {
		tvaddr_t tpc = Rpc + SBRoffset32;
		Rpc = Rnpc;
		Rnpc = tpc;
		return;
	}
	ENDI

#endif	/* } */





	/*
	 * Instruction: sparcv9_bl_icc
	 */

#if !defined(HAS_NATIVE_sparcv9_bl_icc)	/* { */

IMPL(bl_icc)
	int cc = V9_ext_icc(sp->v9_ccr);
	if ( (sparcv9_cc_magic[cond_l] >> cc) &1 ) {
		tvaddr_t tpc = Rpc + SBRoffset32;
		Rpc = Rnpc;
		Rnpc = tpc;
		return;
	}
	ENDI

#endif	/* } */





	/*
	 * Instruction: sparcv9_bgu_icc
	 */

#if !defined(HAS_NATIVE_sparcv9_bgu_icc)	/* { */

IMPL(bgu_icc)
	int cc = V9_ext_icc(sp->v9_ccr);
	if ( (sparcv9_cc_magic[cond_gu] >> cc) &1 ) {
		tvaddr_t tpc = Rpc + SBRoffset32;
		Rpc = Rnpc;
		Rnpc = tpc;
		return;
	}
	ENDI

#endif	/* } */





	/*
	 * Instruction: sparcv9_bleu_icc
	 */

#if !defined(HAS_NATIVE_sparcv9_bleu_icc)	/* { */

IMPL(bleu_icc)
	int cc = V9_ext_icc(sp->v9_ccr);
	if ( (sparcv9_cc_magic[cond_leu] >> cc) &1 ) {
		tvaddr_t tpc = Rpc + SBRoffset32;
		Rpc = Rnpc;
		Rnpc = tpc;
		return;
	}
	ENDI

#endif	/* } */





	/*
	 * Instruction: sparcv9_bcc_icc
	 */

#if !defined(HAS_NATIVE_sparcv9_bcc_icc)	/* { */

IMPL(bcc_icc)
	if ( !(sp->v9_ccr & V9_icc_c_mask) ) {
		tvaddr_t tpc = Rpc + SBRoffset32;
		Rpc = Rnpc;
		Rnpc = tpc;
		return;
	}
	ENDI

#endif	/* } */





	/*
	 * Instruction: sparcv9_bcs_icc
	 */

#if !defined(HAS_NATIVE_sparcv9_bcs_icc)	/* { */

IMPL(bcs_icc)
	if ( sp->v9_ccr & V9_icc_c_mask ) {
		tvaddr_t tpc = Rpc + SBRoffset32;
		Rpc = Rnpc;
		Rnpc = tpc;
		return;
	}
	ENDI

#endif	/* } */





	/*
	 * Instruction: sparcv9_bpos_icc
	 */

#if !defined(HAS_NATIVE_sparcv9_bpos_icc)	/* { */

IMPL(bpos_icc)
	if ( !(sp->v9_ccr & V9_icc_n_mask) ) {
		tvaddr_t tpc = Rpc + SBRoffset32;
		Rpc = Rnpc;
		Rnpc = tpc;
		return;
	}
	ENDI

#endif	/* } */





	/*
	 * Instruction: sparcv9_bneg_icc
	 */

#if !defined(HAS_NATIVE_sparcv9_bneg_icc)	/* { */

IMPL(bneg_icc)
	if ( sp->v9_ccr & V9_icc_n_mask ) {
		tvaddr_t tpc = Rpc + SBRoffset32;
		Rpc = Rnpc;
		Rnpc = tpc;
		return;
	}
	ENDI

#endif	/* } */





	/*
	 * Instruction: sparcv9_bvc_icc
	 */

#if !defined(HAS_NATIVE_sparcv9_bvc_icc)	/* { */

IMPL(bvc_icc)
	if ( !(sp->v9_ccr & V9_icc_v_mask) ) {
		tvaddr_t tpc = Rpc + SBRoffset32;
		Rpc = Rnpc;
		Rnpc = tpc;
		return;
	}
	ENDI

#endif	/* } */





	/*
	 * Instruction: sparcv9_bvs_icc
	 */

#if !defined(HAS_NATIVE_sparcv9_bvs_icc)	/* { */

IMPL(bvs_icc)
	if ( sp->v9_ccr & V9_icc_v_mask ) {
		tvaddr_t tpc = Rpc + SBRoffset32;
		Rpc = Rnpc;
		Rnpc = tpc;
		return;
	}
	ENDI

#endif	/* } */



	/*
	 * Instruction: sparcv9_bne_xcc
	 */

#if !defined(HAS_NATIVE_sparcv9_bne_xcc)	/* { */

IMPL(bne_xcc)
	if (!(sp->v9_ccr & V9_xcc_z_mask)) {
		tvaddr_t tpc = Rpc + SBRoffset32;
		Rpc = Rnpc;
		Rnpc = tpc;
		return;
	}
	ENDI

#endif	/* } */





	/*
	 * Instruction: sparcv9_be_xcc
	 */

#if !defined(HAS_NATIVE_sparcv9_be_xcc)	/* { */

IMPL(be_xcc)
	if (sp->v9_ccr & V9_xcc_z_mask) {
		tvaddr_t tpc = Rpc + SBRoffset32;
		Rpc = Rnpc;
		Rnpc = tpc;
		return;
	}
	ENDI

#endif	/* } */





	/*
	 * Instruction: sparcv9_bg_xcc
	 */

#if !defined(HAS_NATIVE_sparcv9_bg_xcc)	/* { */

IMPL(bg_xcc)
	int cc = V9_ext_xcc(sp->v9_ccr);
	if ( (sparcv9_cc_magic[cond_g] >> cc) &1 ) {
		tvaddr_t tpc = Rpc + SBRoffset32;
		Rpc = Rnpc;
		Rnpc = tpc;
		return;
	}
	ENDI

#endif	/* } */





	/*
	 * Instruction: sparcv9_ble_xcc
	 */

#if !defined(HAS_NATIVE_sparcv9_ble_xcc)	/* { */

IMPL(ble_xcc)
	int cc = V9_ext_xcc(sp->v9_ccr);
	if ( (sparcv9_cc_magic[cond_le] >> cc) &1 ) {
		tvaddr_t tpc = Rpc + SBRoffset32;
		Rpc = Rnpc;
		Rnpc = tpc;
		return;
	}
	ENDI

#endif	/* } */





	/*
	 * Instruction: sparcv9_bge_xcc
	 */

#if !defined(HAS_NATIVE_sparcv9_bge_xcc)	/* { */

IMPL(bge_xcc)
	int cc = V9_ext_xcc(sp->v9_ccr);
	if ( (sparcv9_cc_magic[cond_ge] >> cc) &1 ) {
		tvaddr_t tpc = Rpc + SBRoffset32;
		Rpc = Rnpc;
		Rnpc = tpc;
		return;
	}
	ENDI

#endif	/* } */





	/*
	 * Instruction: sparcv9_bl_xcc
	 */

#if !defined(HAS_NATIVE_sparcv9_bl_xcc)	/* { */

IMPL(bl_xcc)
	int cc = V9_ext_xcc(sp->v9_ccr);
	if ( (sparcv9_cc_magic[cond_l] >> cc) &1 ) {
		tvaddr_t tpc = Rpc + SBRoffset32;
		Rpc = Rnpc;
		Rnpc = tpc;
		return;
	}
	ENDI

#endif	/* } */





	/*
	 * Instruction: sparcv9_bgu_xcc
	 */

#if !defined(HAS_NATIVE_sparcv9_bgu_xcc)	/* { */

IMPL(bgu_xcc)
	int cc = V9_ext_xcc(sp->v9_ccr);
	if ( (sparcv9_cc_magic[cond_gu] >> cc) &1 ) {
		tvaddr_t tpc = Rpc + SBRoffset32;
		Rpc = Rnpc;
		Rnpc = tpc;
		return;
	}
	ENDI

#endif	/* } */





	/*
	 * Instruction: sparcv9_bleu_xcc
	 */

#if !defined(HAS_NATIVE_sparcv9_bleu_xcc)	/* { */

IMPL(bleu_xcc)
	int cc = V9_ext_xcc(sp->v9_ccr);
	if ( (sparcv9_cc_magic[cond_leu] >> cc) &1 ) {
		tvaddr_t tpc = Rpc + SBRoffset32;
		Rpc = Rnpc;
		Rnpc = tpc;
		return;
	}
	ENDI

#endif	/* } */





	/*
	 * Instruction: sparcv9_bcc_xcc
	 */

#if !defined(HAS_NATIVE_sparcv9_bcc_xcc)	/* { */

IMPL(bcc_xcc)
	if ( !(sp->v9_ccr & V9_xcc_c_mask) ) {
		tvaddr_t tpc = Rpc + SBRoffset32;
		Rpc = Rnpc;
		Rnpc = tpc;
		return;
	}
	ENDI

#endif	/* } */





	/*
	 * Instruction: sparcv9_bcs_xcc
	 */

#if !defined(HAS_NATIVE_sparcv9_bcs_xcc)	/* { */

IMPL(bcs_xcc)
	if ( sp->v9_ccr & V9_xcc_c_mask ) {
		tvaddr_t tpc = Rpc + SBRoffset32;
		Rpc = Rnpc;
		Rnpc = tpc;
		return;
	}
	ENDI

#endif	/* } */





	/*
	 * Instruction: sparcv9_bpos_xcc
	 */

#if !defined(HAS_NATIVE_sparcv9_bpos_xcc)	/* { */

IMPL(bpos_xcc)
	if ( !(sp->v9_ccr & V9_xcc_n_mask) ) {
		tvaddr_t tpc = Rpc + SBRoffset32;
		Rpc = Rnpc;
		Rnpc = tpc;
		return;
	}
	ENDI

#endif	/* } */





	/*
	 * Instruction: sparcv9_bneg_xcc
	 */

#if !defined(HAS_NATIVE_sparcv9_bneg_xcc)	/* { */

IMPL(bneg_xcc)
	if ( sp->v9_ccr & V9_xcc_n_mask ) {
		tvaddr_t tpc = Rpc + SBRoffset32;
		Rpc = Rnpc;
		Rnpc = tpc;
		return;
	}
	ENDI

#endif	/* } */





	/*
	 * Instruction: sparcv9_bvc_xcc
	 */

#if !defined(HAS_NATIVE_sparcv9_bvc_xcc)	/* { */

IMPL(bvc_xcc)
	if ( !(sp->v9_ccr & V9_xcc_v_mask) ) {
		tvaddr_t tpc = Rpc + SBRoffset32;
		Rpc = Rnpc;
		Rnpc = tpc;
		return;
	}
	ENDI

#endif	/* } */





	/*
	 * Instruction: sparcv9_bvs_xcc
	 */

#if !defined(HAS_NATIVE_sparcv9_bvs_xcc)	/* { */

IMPL(bvs_xcc)
	if ( sp->v9_ccr & V9_xcc_v_mask ) {
		tvaddr_t tpc = Rpc + SBRoffset32;
		Rpc = Rnpc;
		Rnpc = tpc;
		return;
	}
	ENDI

#endif	/* } */








	/*
	 * Instruction: sparcv9_bne_icc_an
	 */

#if !defined(HAS_NATIVE_sparcv9_bne_icc_an)	/* { */

IMPL(bne_icc_an)
	if (!(sp->v9_ccr & V9_icc_z_mask)) {
		tvaddr_t tpc = Rpc + SBRoffset32;
		Rpc = Rnpc;
		Rnpc = tpc;
		return;
	}
	Rpc = Rnpc + 4;
	Rnpc = Rnpc + 8;
	ENDDEF

#endif	/* } */





	/*
	 * Instruction: sparcv9_be_icc_an
	 */

#if !defined(HAS_NATIVE_sparcv9_be_icc_an)	/* { */

IMPL(be_icc_an)
	if (sp->v9_ccr & V9_icc_z_mask) {
		tvaddr_t tpc = Rpc + SBRoffset32;
		Rpc = Rnpc;
		Rnpc = tpc;
		return;
	}
	Rpc = Rnpc + 4;
	Rnpc = Rnpc + 8;
	ENDDEF

#endif	/* } */





	/*
	 * Instruction: sparcv9_bg_icc_an
	 */

#if !defined(HAS_NATIVE_sparcv9_bg_icc_an)	/* { */

IMPL(bg_icc_an)
	int cc = V9_ext_icc(sp->v9_ccr);
	if ( (sparcv9_cc_magic[cond_g] >> cc) &1 ) {
		tvaddr_t tpc = Rpc + SBRoffset32;
		Rpc = Rnpc;
		Rnpc = tpc;
		return;
	}
	Rpc = Rnpc + 4;
	Rnpc = Rnpc + 8;
	ENDDEF

#endif	/* } */





	/*
	 * Instruction: sparcv9_ble_icc_an
	 */

#if !defined(HAS_NATIVE_sparcv9_ble_icc_an)	/* { */

IMPL(ble_icc_an)
	int cc = V9_ext_icc(sp->v9_ccr);
	if ( (sparcv9_cc_magic[cond_le] >> cc) &1 ) {
		tvaddr_t tpc = Rpc + SBRoffset32;
		Rpc = Rnpc;
		Rnpc = tpc;
		return;
	}
	Rpc = Rnpc + 4;
	Rnpc = Rnpc + 8;
	ENDDEF

#endif	/* } */





	/*
	 * Instruction: sparcv9_bge_icc_an
	 */

#if !defined(HAS_NATIVE_sparcv9_bge_icc_an)	/* { */

IMPL(bge_icc_an)
	int cc = V9_ext_icc(sp->v9_ccr);
	if ( (sparcv9_cc_magic[cond_ge] >> cc) &1 ) {
		tvaddr_t tpc = Rpc + SBRoffset32;
		Rpc = Rnpc;
		Rnpc = tpc;
		return;
	}
	Rpc = Rnpc + 4;
	Rnpc = Rnpc + 8;
	ENDDEF

#endif	/* } */





	/*
	 * Instruction: sparcv9_bl_icc_an
	 */

#if !defined(HAS_NATIVE_sparcv9_bl_icc_an)	/* { */

IMPL(bl_icc_an)
	int cc = V9_ext_icc(sp->v9_ccr);
	if ( (sparcv9_cc_magic[cond_l] >> cc) &1 ) {
		tvaddr_t tpc = Rpc + SBRoffset32;
		Rpc = Rnpc;
		Rnpc = tpc;
		return;
	}
	Rpc = Rnpc + 4;
	Rnpc = Rnpc + 8;
	ENDDEF

#endif	/* } */





	/*
	 * Instruction: sparcv9_bgu_icc_an
	 */

#if !defined(HAS_NATIVE_sparcv9_bgu_icc_an)	/* { */

IMPL(bgu_icc_an)
	int cc = V9_ext_icc(sp->v9_ccr);
	if ( (sparcv9_cc_magic[cond_gu] >> cc) &1 ) {
		tvaddr_t tpc = Rpc + SBRoffset32;
		Rpc = Rnpc;
		Rnpc = tpc;
		return;
	}
	Rpc = Rnpc + 4;
	Rnpc = Rnpc + 8;
	ENDDEF

#endif	/* } */





	/*
	 * Instruction: sparcv9_bleu_icc_an
	 */

#if !defined(HAS_NATIVE_sparcv9_bleu_icc_an)	/* { */

IMPL(bleu_icc_an)
	int cc = V9_ext_icc(sp->v9_ccr);
	if ( (sparcv9_cc_magic[cond_leu] >> cc) &1 ) {
		tvaddr_t tpc = Rpc + SBRoffset32;
		Rpc = Rnpc;
		Rnpc = tpc;
		return;
	}
	Rpc = Rnpc + 4;
	Rnpc = Rnpc + 8;
	ENDDEF

#endif	/* } */





	/*
	 * Instruction: sparcv9_bcc_icc_an
	 */

#if !defined(HAS_NATIVE_sparcv9_bcc_icc_an)	/* { */

IMPL(bcc_icc_an)
	if ( !(sp->v9_ccr & V9_icc_c_mask) ) {
		tvaddr_t tpc = Rpc + SBRoffset32;
		Rpc = Rnpc;
		Rnpc = tpc;
		return;
	}
	Rpc = Rnpc + 4;
	Rnpc = Rnpc + 8;
	ENDDEF

#endif	/* } */





	/*
	 * Instruction: sparcv9_bcs_icc_an
	 */

#if !defined(HAS_NATIVE_sparcv9_bcs_icc_an)	/* { */

IMPL(bcs_icc_an)
	if ( sp->v9_ccr & V9_icc_c_mask ) {
		tvaddr_t tpc = Rpc + SBRoffset32;
		Rpc = Rnpc;
		Rnpc = tpc;
		return;
	}
	Rpc = Rnpc + 4;
	Rnpc = Rnpc + 8;
	ENDDEF

#endif	/* } */





	/*
	 * Instruction: sparcv9_bpos_icc_an
	 */

#if !defined(HAS_NATIVE_sparcv9_bpos_icc_an)	/* { */

IMPL(bpos_icc_an)
	if ( !(sp->v9_ccr & V9_icc_n_mask) ) {
		tvaddr_t tpc = Rpc + SBRoffset32;
		Rpc = Rnpc;
		Rnpc = tpc;
		return;
	}
	Rpc = Rnpc + 4;
	Rnpc = Rnpc + 8;
	ENDDEF

#endif	/* } */





	/*
	 * Instruction: sparcv9_bneg_icc_an
	 */

#if !defined(HAS_NATIVE_sparcv9_bneg_icc_an)	/* { */

IMPL(bneg_icc_an)
	if ( sp->v9_ccr & V9_icc_n_mask ) {
		tvaddr_t tpc = Rpc + SBRoffset32;
		Rpc = Rnpc;
		Rnpc = tpc;
		return;
	}
	Rpc = Rnpc + 4;
	Rnpc = Rnpc + 8;
	ENDDEF

#endif	/* } */





	/*
	 * Instruction: sparcv9_bvc_icc_an
	 */

#if !defined(HAS_NATIVE_sparcv9_bvc_icc_an)	/* { */

IMPL(bvc_icc_an)
	if ( !(sp->v9_ccr & V9_icc_v_mask) ) {
		tvaddr_t tpc = Rpc + SBRoffset32;
		Rpc = Rnpc;
		Rnpc = tpc;
		return;
	}
	Rpc = Rnpc + 4;
	Rnpc = Rnpc + 8;
	ENDDEF

#endif	/* } */





	/*
	 * Instruction: sparcv9_bvs_icc_an
	 */

#if !defined(HAS_NATIVE_sparcv9_bvs_icc_an)	/* { */

IMPL(bvs_icc_an)
	if ( sp->v9_ccr & V9_icc_v_mask ) {
		tvaddr_t tpc = Rpc + SBRoffset32;
		Rpc = Rnpc;
		Rnpc = tpc;
		return;
	}
	Rpc = Rnpc + 4;
	Rnpc = Rnpc + 8;
	ENDDEF

#endif	/* } */






	/*
	 * Instruction: sparcv9_bne_xcc_an
	 */

#if !defined(HAS_NATIVE_sparcv9_bne_xcc_an)	/* { */

IMPL(bne_xcc_an)
	if (!(sp->v9_ccr & V9_xcc_z_mask)) {
		tvaddr_t tpc = Rpc + SBRoffset32;
		Rpc = Rnpc;
		Rnpc = tpc;
		return;
	}
	Rpc = Rnpc + 4;
	Rnpc = Rnpc + 8;
	ENDDEF

#endif	/* } */





	/*
	 * Instruction: sparcv9_be_xcc_an
	 */

#if !defined(HAS_NATIVE_sparcv9_be_xcc_an)	/* { */

IMPL(be_xcc_an)
	if (sp->v9_ccr & V9_xcc_z_mask) {
		tvaddr_t tpc = Rpc + SBRoffset32;
		Rpc = Rnpc;
		Rnpc = tpc;
		return;
	}
	Rpc = Rnpc + 4;
	Rnpc = Rnpc + 8;
	ENDDEF

#endif	/* } */





	/*
	 * Instruction: sparcv9_bg_xcc_an
	 */

#if !defined(HAS_NATIVE_sparcv9_bg_xcc_an)	/* { */

IMPL(bg_xcc_an)
	int cc = V9_ext_xcc(sp->v9_ccr);
	if ( (sparcv9_cc_magic[cond_g] >> cc) &1 ) {
		tvaddr_t tpc = Rpc + SBRoffset32;
		Rpc = Rnpc;
		Rnpc = tpc;
		return;
	}
	Rpc = Rnpc + 4;
	Rnpc = Rnpc + 8;
	ENDDEF

#endif	/* } */





	/*
	 * Instruction: sparcv9_ble_xcc_an
	 */

#if !defined(HAS_NATIVE_sparcv9_ble_xcc_an)	/* { */

IMPL(ble_xcc_an)
	int cc = V9_ext_xcc(sp->v9_ccr);
	if ( (sparcv9_cc_magic[cond_le] >> cc) &1 ) {
		tvaddr_t tpc = Rpc + SBRoffset32;
		Rpc = Rnpc;
		Rnpc = tpc;
		return;
	}
	Rpc = Rnpc + 4;
	Rnpc = Rnpc + 8;
	ENDDEF

#endif	/* } */





	/*
	 * Instruction: sparcv9_bge_xcc_an
	 */

#if !defined(HAS_NATIVE_sparcv9_bge_xcc_an)	/* { */

IMPL(bge_xcc_an)
	int cc = V9_ext_xcc(sp->v9_ccr);
	if ( (sparcv9_cc_magic[cond_ge] >> cc) &1 ) {
		tvaddr_t tpc = Rpc + SBRoffset32;
		Rpc = Rnpc;
		Rnpc = tpc;
		return;
	}
	Rpc = Rnpc + 4;
	Rnpc = Rnpc + 8;
	ENDDEF

#endif	/* } */





	/*
	 * Instruction: sparcv9_bl_xcc_an
	 */

#if !defined(HAS_NATIVE_sparcv9_bl_xcc_an)	/* { */

IMPL(bl_xcc_an)
	int cc = V9_ext_xcc(sp->v9_ccr);
	if ( (sparcv9_cc_magic[cond_l] >> cc) &1 ) {
		tvaddr_t tpc = Rpc + SBRoffset32;
		Rpc = Rnpc;
		Rnpc = tpc;
		return;
	}
	Rpc = Rnpc + 4;
	Rnpc = Rnpc + 8;
	ENDDEF

#endif	/* } */





	/*
	 * Instruction: sparcv9_bgu_xcc_an
	 */

#if !defined(HAS_NATIVE_sparcv9_bgu_xcc_an)	/* { */

IMPL(bgu_xcc_an)
	int cc = V9_ext_xcc(sp->v9_ccr);
	if ( (sparcv9_cc_magic[cond_gu] >> cc) &1 ) {
		tvaddr_t tpc = Rpc + SBRoffset32;
		Rpc = Rnpc;
		Rnpc = tpc;
		return;
	}
	Rpc = Rnpc + 4;
	Rnpc = Rnpc + 8;
	ENDDEF

#endif	/* } */





	/*
	 * Instruction: sparcv9_bleu_xcc_an
	 */

#if !defined(HAS_NATIVE_sparcv9_bleu_xcc_an)	/* { */

IMPL(bleu_xcc_an)
	int cc = V9_ext_xcc(sp->v9_ccr);
	if ( (sparcv9_cc_magic[cond_leu] >> cc) &1 ) {
		tvaddr_t tpc = Rpc + SBRoffset32;
		Rpc = Rnpc;
		Rnpc = tpc;
		return;
	}
	Rpc = Rnpc + 4;
	Rnpc = Rnpc + 8;
	ENDDEF

#endif	/* } */





	/*
	 * Instruction: sparcv9_bcc_xcc_an
	 */

#if !defined(HAS_NATIVE_sparcv9_bcc_xcc_an)	/* { */

IMPL(bcc_xcc_an)
	if ( !(sp->v9_ccr & V9_xcc_c_mask) ) {
		tvaddr_t tpc = Rpc + SBRoffset32;
		Rpc = Rnpc;
		Rnpc = tpc;
		return;
	}
	Rpc = Rnpc + 4;
	Rnpc = Rnpc + 8;
	ENDDEF

#endif	/* } */





	/*
	 * Instruction: sparcv9_bcs_xcc_an
	 */

#if !defined(HAS_NATIVE_sparcv9_bcs_xcc_an)	/* { */

IMPL(bcs_xcc_an)
	if ( sp->v9_ccr & V9_xcc_c_mask ) {
		tvaddr_t tpc = Rpc + SBRoffset32;
		Rpc = Rnpc;
		Rnpc = tpc;
		return;
	}
	Rpc = Rnpc + 4;
	Rnpc = Rnpc + 8;
	ENDDEF

#endif	/* } */





	/*
	 * Instruction: sparcv9_bpos_xcc_an
	 */

#if !defined(HAS_NATIVE_sparcv9_bpos_xcc_an)	/* { */

IMPL(bpos_xcc_an)
	if ( !(sp->v9_ccr & V9_xcc_n_mask) ) {
		tvaddr_t tpc = Rpc + SBRoffset32;
		Rpc = Rnpc;
		Rnpc = tpc;
		return;
	}
	Rpc = Rnpc + 4;
	Rnpc = Rnpc + 8;
	ENDDEF

#endif	/* } */





	/*
	 * Instruction: sparcv9_bneg_xcc_an
	 */

#if !defined(HAS_NATIVE_sparcv9_bneg_xcc_an)	/* { */

IMPL(bneg_xcc_an)
	if ( sp->v9_ccr & V9_xcc_n_mask ) {
		tvaddr_t tpc = Rpc + SBRoffset32;
		Rpc = Rnpc;
		Rnpc = tpc;
		return;
	}
	Rpc = Rnpc + 4;
	Rnpc = Rnpc + 8;
	ENDDEF

#endif	/* } */





	/*
	 * Instruction: sparcv9_bvc_xcc_an
	 */

#if !defined(HAS_NATIVE_sparcv9_bvc_xcc_an)	/* { */

IMPL(bvc_xcc_an)
	if ( !(sp->v9_ccr & V9_xcc_v_mask) ) {
		tvaddr_t tpc = Rpc + SBRoffset32;
		Rpc = Rnpc;
		Rnpc = tpc;
		return;
	}
	Rpc = Rnpc + 4;
	Rnpc = Rnpc + 8;
	ENDDEF

#endif	/* } */





	/*
	 * Instruction: sparcv9_bvs_xcc_an
	 */

#if !defined(HAS_NATIVE_sparcv9_bvs_xcc_an)	/* { */

IMPL(bvs_xcc_an)
	if ( sp->v9_ccr & V9_xcc_v_mask ) {
		tvaddr_t tpc = Rpc + SBRoffset32;
		Rpc = Rnpc;
		Rnpc = tpc;
		return;
	}
	Rpc = Rnpc + 4;
	Rnpc = Rnpc + 8;
	ENDDEF

#endif	/* } */










	/*
	 * Instruction: sparcv9_brz
	 */

#if !defined(HAS_NATIVE_sparcv9_brz)	/* { */

IMPL(brz)
	if (0ULL == Rsrc1) {
		tvaddr_t tpc = Rpc + SBRreg_off32;
		Rpc = Rnpc;
		Rnpc = tpc;
		return;
	}
	ENDI

#endif	/* } */





	/*
	 * Instruction: sparcv9_brlez
	 */

#if !defined(HAS_NATIVE_sparcv9_brlez)	/* { */

IMPL(brlez)
	if (SRsrc1 <= 0LL) {
		tvaddr_t tpc = Rpc + SBRreg_off32;
		Rpc = Rnpc;
		Rnpc = tpc;
		return;
	}
	ENDI

#endif	/* } */





	/*
	 * Instruction: sparcv9_brlz
	 */

#if !defined(HAS_NATIVE_sparcv9_brlz)	/* { */

IMPL(brlz)
	if (SRsrc1 < 0LL) {
		tvaddr_t tpc = Rpc + SBRreg_off32;
		Rpc = Rnpc;
		Rnpc = tpc;
		return;
	}
	ENDI

#endif	/* } */





	/*
	 * Instruction: sparcv9_brnz
	 */

#if !defined(HAS_NATIVE_sparcv9_brnz)	/* { */

IMPL(brnz)
	if (SRsrc1 != 0LL) {
		tvaddr_t tpc = Rpc + SBRreg_off32;
		Rpc = Rnpc;
		Rnpc = tpc;
		return;
	}
	ENDI

#endif	/* } */





	/*
	 * Instruction: sparcv9_brgz
	 */

#if !defined(HAS_NATIVE_sparcv9_brgz)	/* { */

IMPL(brgz)
	if (SRsrc1 > 0LL) {
		tvaddr_t tpc = Rpc + SBRreg_off32;
		Rpc = Rnpc;
		Rnpc = tpc;
		return;
	}
	ENDI

#endif	/* } */





	/*
	 * Instruction: sparcv9_brgez
	 */

#if !defined(HAS_NATIVE_sparcv9_brgez)	/* { */

IMPL(brgez)
	if (SRsrc1 >= 0LL) {
		tvaddr_t tpc = Rpc + SBRreg_off32;
		Rpc = Rnpc;
		Rnpc = tpc;
		return;
	}
	ENDI

#endif	/* } */





	/*
	 * Instruction: sparcv9_brz_an
	 */

#if !defined(HAS_NATIVE_sparcv9_brz_an)	/* { */

IMPL(brz_an)
	if ( Rsrc1 == 0LL ) {
		tvaddr_t tpc = Rpc + SBRreg_off32;
		Rpc = Rnpc;
		Rnpc = tpc;
		return;
	}
	Rpc = Rnpc + 4;
	Rnpc = Rnpc + 8;
	ENDDEF

#endif	/* } */





	/*
	 * Instruction: sparcv9_brlez_an
	 */

#if !defined(HAS_NATIVE_sparcv9_brlez_an)	/* { */

IMPL(brlez_an)
	if ( SRsrc1 <= 0LL ) {
		tvaddr_t tpc = Rpc + SBRreg_off32;
		Rpc = Rnpc;
		Rnpc = tpc;
		return;
	}
	Rpc = Rnpc + 4;
	Rnpc = Rnpc + 8;
	ENDDEF

#endif	/* } */





	/*
	 * Instruction: sparcv9_brlz_an
	 */

#if !defined(HAS_NATIVE_sparcv9_brlz_an)	/* { */

IMPL(brlz_an)
	if ( SRsrc1 < 0LL ) {
		tvaddr_t tpc = Rpc + SBRreg_off32;
		Rpc = Rnpc;
		Rnpc = tpc;
		return;
	}
	Rpc = Rnpc + 4;
	Rnpc = Rnpc + 8;
	ENDDEF

#endif	/* } */





	/*
	 * Instruction: sparcv9_brnz_an
	 */

#if !defined(HAS_NATIVE_sparcv9_brnz_an)	/* { */

IMPL(brnz_an)
	if ( SRsrc1 != 0LL ) {
		tvaddr_t tpc = Rpc + SBRreg_off32;
		Rpc = Rnpc;
		Rnpc = tpc;
		return;
	}
	Rpc = Rnpc + 4;
	Rnpc = Rnpc + 8;
	ENDDEF

#endif	/* } */





	/*
	 * Instruction: sparcv9_brgz_an
	 */

#if !defined(HAS_NATIVE_sparcv9_brgz_an)	/* { */

IMPL(brgz_an)
	if ( SRsrc1 > 0LL ) {
		tvaddr_t tpc = Rpc + SBRreg_off32;
		Rpc = Rnpc;
		Rnpc = tpc;
		return;
	}
	Rpc = Rnpc + 4;
	Rnpc = Rnpc + 8;
	ENDDEF

#endif	/* } */





	/*
	 * Instruction: sparcv9_brgez_an
	 */

#if !defined(HAS_NATIVE_sparcv9_brgez_an)	/* { */

IMPL(brgez_an)
	if ( SRsrc1 >= 0LL ) {
		tvaddr_t tpc = Rpc + SBRreg_off32;
		Rpc = Rnpc;
		Rnpc = tpc;
		return;
	}
	Rpc = Rnpc + 4;
	Rnpc = Rnpc + 8;
	ENDDEF

#endif	/* } */





	/*
	 * Instruction: sparcv9_fadds
	 */

#if !defined(HAS_NATIVE_sparcv9_fadds)	/* { */

IMPL(fadds)
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
#ifndef FP_DECODE_DISABLED
	if (!v9p->fpu_on) {
		v9p->post_precise_trap(sp, Sparcv9_trap_fp_disabled);
		return;
	}
#endif /* FP_DECODE_DISABLED */
	FIXME_WARNING(("non-native implementation of fadds (sparcv9_fadds) not yet completed")); exit(0);
	ENDI

#endif	/* } */





	/*
	 * Instruction: sparcv9_faddd
	 */

#if !defined(HAS_NATIVE_sparcv9_faddd)	/* { */

IMPL(faddd)
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
#ifndef FP_DECODE_DISABLED
	if (!v9p->fpu_on) {
		v9p->post_precise_trap(sp, Sparcv9_trap_fp_disabled);
		return;
	}
#endif /* FP_DECODE_DISABLED */
	FIXME_WARNING(("non-native implementation of faddd (sparcv9_faddd) not yet completed")); exit(0);
	ENDI

#endif	/* } */





	/*
	 * Instruction: sparcv9_faddq
	 */

#if !defined(HAS_NATIVE_sparcv9_faddq)	/* { */

IMPL(faddq)
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
#ifndef FP_DECODE_DISABLED
	if (!v9p->fpu_on) {
		v9p->post_precise_trap(sp, Sparcv9_trap_fp_disabled);
		return;
	}
#endif /* FP_DECODE_DISABLED */
	FIXME_WARNING(("non-native implementation of faddq (sparcv9_faddq) not yet completed")); exit(0);
	ENDI

#endif	/* } */





	/*
	 * Instruction: sparcv9_fsubs
	 */

#if !defined(HAS_NATIVE_sparcv9_fsubs)	/* { */

IMPL(fsubs)
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
#ifndef FP_DECODE_DISABLED
	if (!v9p->fpu_on) {
		v9p->post_precise_trap(sp, Sparcv9_trap_fp_disabled);
		return;
	}
#endif /* FP_DECODE_DISABLED */
	FIXME_WARNING(("non-native implementation of fsubs (sparcv9_fsubs) not yet completed")); exit(0);
	ENDI

#endif	/* } */





	/*
	 * Instruction: sparcv9_fsubd
	 */

#if !defined(HAS_NATIVE_sparcv9_fsubd)	/* { */

IMPL(fsubd)
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
#ifndef FP_DECODE_DISABLED
	if (!v9p->fpu_on) {
		v9p->post_precise_trap(sp, Sparcv9_trap_fp_disabled);
		return;
	}
#endif /* FP_DECODE_DISABLED */
	FIXME_WARNING(("non-native implementation of fsubd (sparcv9_fsubd) not yet completed")); exit(0);
	ENDI

#endif	/* } */





	/*
	 * Instruction: sparcv9_fsubq
	 */

#if !defined(HAS_NATIVE_sparcv9_fsubq)	/* { */

IMPL(fsubq)
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
#ifndef FP_DECODE_DISABLED
	if (!v9p->fpu_on) {
		v9p->post_precise_trap(sp, Sparcv9_trap_fp_disabled);
		return;
	}
#endif /* FP_DECODE_DISABLED */
	FIXME_WARNING(("non-native implementation of fsubq (sparcv9_fsubq) not yet completed")); exit(0);
	ENDI

#endif	/* } */





	/*
	 * Instruction: sparcv9_fmuls
	 */

#if !defined(HAS_NATIVE_sparcv9_fmuls)	/* { */

IMPL(fmuls)
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
#ifndef FP_DECODE_DISABLED
	if (!v9p->fpu_on) {
		v9p->post_precise_trap(sp, Sparcv9_trap_fp_disabled);
		return;
	}
#endif /* FP_DECODE_DISABLED */
	FIXME_WARNING(("non-native implementation of fmuls (sparcv9_fmuls) not yet completed")); exit(0);
	ENDI

#endif	/* } */





	/*
	 * Instruction: sparcv9_fmuld
	 */

#if !defined(HAS_NATIVE_sparcv9_fmuld)	/* { */

IMPL(fmuld)
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
#ifndef FP_DECODE_DISABLED
	if (!v9p->fpu_on) {
		v9p->post_precise_trap(sp, Sparcv9_trap_fp_disabled);
		return;
	}
#endif /* FP_DECODE_DISABLED */
	FIXME_WARNING(("non-native implementation of fmuld (sparcv9_fmuld) not yet completed")); exit(0);
	ENDI

#endif	/* } */





	/*
	 * Instruction: sparcv9_fmulq
	 */

#if !defined(HAS_NATIVE_sparcv9_fmulq)	/* { */

IMPL(fmulq)
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
#ifndef FP_DECODE_DISABLED
	if (!v9p->fpu_on) {
		v9p->post_precise_trap(sp, Sparcv9_trap_fp_disabled);
		return;
	}
#endif /* FP_DECODE_DISABLED */
	FIXME_WARNING(("non-native implementation of fmulq (sparcv9_fmulq) not yet completed")); exit(0);
	ENDI

#endif	/* } */





	/*
	 * Instruction: sparcv9_fdivs
	 */

#if !defined(HAS_NATIVE_sparcv9_fdivs)	/* { */

IMPL(fdivs)
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
#ifndef FP_DECODE_DISABLED
	if (!v9p->fpu_on) {
		v9p->post_precise_trap(sp, Sparcv9_trap_fp_disabled);
		return;
	}
#endif /* FP_DECODE_DISABLED */
	FIXME_WARNING(("non-native implementation of fdivs (sparcv9_fdivs) not yet completed")); exit(0);
	ENDI

#endif	/* } */





	/*
	 * Instruction: sparcv9_fdivd
	 */

#if !defined(HAS_NATIVE_sparcv9_fdivd)	/* { */

IMPL(fdivd)
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
#ifndef FP_DECODE_DISABLED
	if (!v9p->fpu_on) {
		v9p->post_precise_trap(sp, Sparcv9_trap_fp_disabled);
		return;
	}
#endif /* FP_DECODE_DISABLED */
	FIXME_WARNING(("non-native implementation of fdivd (sparcv9_fdivd) not yet completed")); exit(0);
	ENDI

#endif	/* } */



	/*
	 * Instruction: sparcv9_fdivq
	 */

#if !defined(HAS_NATIVE_sparcv9_fdivq)	/* { */

IMPL(fdivq)
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
#ifndef FP_DECODE_DISABLED
	if (!v9p->fpu_on) {
		v9p->post_precise_trap(sp, Sparcv9_trap_fp_disabled);
		return;
	}
#endif /* FP_DECODE_DISABLED */
	FIXME_WARNING(("non-native implementation of fdivq (sparcv9_fdivq) not yet completed")); exit(0);
	ENDI

#endif	/* } */





	/*
	 * Instruction: sparcv9_fsmuld
	 */

#if !defined(HAS_NATIVE_sparcv9_fsmuld)	/* { */

IMPL(fsmuld)
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
#ifndef FP_DECODE_DISABLED
	if (!v9p->fpu_on) {
		v9p->post_precise_trap(sp, Sparcv9_trap_fp_disabled);
		return;
	}
#endif /* FP_DECODE_DISABLED */
	FIXME_WARNING(("non-native implementation of fsmuld (sparcv9_fsmuld) not yet completed")); exit(0);
	ENDI

#endif	/* } */





	/*
	 * Instruction: sparcv9_fdmulq
	 */

#if !defined(HAS_NATIVE_sparcv9_fdmulq)	/* { */

IMPL(fdmulq)
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
#ifndef FP_DECODE_DISABLED
	if (!v9p->fpu_on) {
		v9p->post_precise_trap(sp, Sparcv9_trap_fp_disabled);
		return;
	}
#endif /* FP_DECODE_DISABLED */
	FIXME_WARNING(("non-native implementation of fdmulq (sparcv9_fdmulq) not yet completed")); exit(0);
	ENDI

#endif	/* } */





	/*
	 * Instruction: sparcv9_fstod
	 */

#if !defined(HAS_NATIVE_sparcv9_fstod)	/* { */

IMPL(fstod)
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
#ifndef FP_DECODE_DISABLED
	if (!v9p->fpu_on) {
		v9p->post_precise_trap(sp, Sparcv9_trap_fp_disabled);
		return;
	}
#endif /* FP_DECODE_DISABLED */
	FIXME_WARNING(("non-native implementation of fstod (sparcv9_fstod) not yet completed")); exit(0);
	ENDI

#endif	/* } */





	/*
	 * Instruction: sparcv9_fstoq
	 */

#if !defined(HAS_NATIVE_sparcv9_fstoq)	/* { */

IMPL(fstoq)
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
#ifndef FP_DECODE_DISABLED
	if (!v9p->fpu_on) {
		v9p->post_precise_trap(sp, Sparcv9_trap_fp_disabled);
		return;
	}
#endif /* FP_DECODE_DISABLED */
	FIXME_WARNING(("non-native implementation of fstoq (sparcv9_fstoq) not yet completed")); exit(0);
	ENDI

#endif	/* } */





	/*
	 * Instruction: sparcv9_fdtos
	 */

#if !defined(HAS_NATIVE_sparcv9_fdtos)	/* { */

IMPL(fdtos)
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
#ifndef FP_DECODE_DISABLED
	if (!v9p->fpu_on) {
		v9p->post_precise_trap(sp, Sparcv9_trap_fp_disabled);
		return;
	}
#endif /* FP_DECODE_DISABLED */
	FIXME_WARNING(("non-native implementation of fdtos (sparcv9_fdtos) not yet completed")); exit(0);
	ENDI

#endif	/* } */





	/*
	 * Instruction: sparcv9_fdtoq
	 */

#if !defined(HAS_NATIVE_sparcv9_fdtoq)	/* { */

IMPL(fdtoq)
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
#ifndef FP_DECODE_DISABLED
	if (!v9p->fpu_on) {
		v9p->post_precise_trap(sp, Sparcv9_trap_fp_disabled);
		return;
	}
#endif /* FP_DECODE_DISABLED */
	FIXME_WARNING(("non-native implementation of fdtoq (sparcv9_fdtoq) not yet completed")); exit(0);
	ENDI

#endif	/* } */





	/*
	 * Instruction: sparcv9_fqtos
	 */

#if !defined(HAS_NATIVE_sparcv9_fqtos)	/* { */

IMPL(fqtos)
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
#ifndef FP_DECODE_DISABLED
	if (!v9p->fpu_on) {
		v9p->post_precise_trap(sp, Sparcv9_trap_fp_disabled);
		return;
	}
#endif /* FP_DECODE_DISABLED */
	FIXME_WARNING(("non-native implementation of fqtos (sparcv9_fqtos) not yet completed")); exit(0);
	ENDI

#endif	/* } */





	/*
	 * Instruction: sparcv9_fqtod
	 */

#if !defined(HAS_NATIVE_sparcv9_fqtod)	/* { */

IMPL(fqtod)
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
#ifndef FP_DECODE_DISABLED
	if (!v9p->fpu_on) {
		v9p->post_precise_trap(sp, Sparcv9_trap_fp_disabled);
		return;
	}
#endif /* FP_DECODE_DISABLED */
	FIXME_WARNING(("non-native implementation of fqtod (sparcv9_fqtod) not yet completed")); exit(0);
	ENDI

#endif	/* } */





	/*
	 * Instruction: sparcv9_fsqrts
	 */

#if !defined(HAS_NATIVE_sparcv9_fsqrts)	/* { */

IMPL(fsqrts)
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
#ifndef FP_DECODE_DISABLED
	if (!v9p->fpu_on) {
		v9p->post_precise_trap(sp, Sparcv9_trap_fp_disabled);
		return;
	}
#endif /* FP_DECODE_DISABLED */
	FIXME_WARNING(("non-native implementation of fsqrts (sparcv9_fsqrts) not yet completed")); exit(0);
	ENDI

#endif	/* } */





	/*
	 * Instruction: sparcv9_fsqrtd
	 */

#if !defined(HAS_NATIVE_sparcv9_fsqrtd)	/* { */

IMPL(fsqrtd)
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
#ifndef FP_DECODE_DISABLED
	if (!v9p->fpu_on) {
		v9p->post_precise_trap(sp, Sparcv9_trap_fp_disabled);
		return;
	}
#endif /* FP_DECODE_DISABLED */
	FIXME_WARNING(("non-native implementation of fsqrtd (sparcv9_fsqrtd) not yet completed")); exit(0);
	ENDI

#endif	/* } */





	/*
	 * Instruction: sparcv9_fsqrtq
	 */

#if !defined(HAS_NATIVE_sparcv9_fsqrtq)	/* { */

IMPL(fsqrtq)
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
#ifndef FP_DECODE_DISABLED
	if (!v9p->fpu_on) {
		v9p->post_precise_trap(sp, Sparcv9_trap_fp_disabled);
		return;
	}
#endif /* FP_DECODE_DISABLED */
	FIXME_WARNING(("non-native implementation of fsqrtq (sparcv9_fsqrtq) not yet completed")); exit(0);
	ENDI

#endif	/* } */





	/*
	 * Instruction: sparcv9_fmovs
	 */

#if !defined(HAS_NATIVE_sparcv9_fmovs)	/* { */

IMPL(fmovs)
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
#ifndef FP_DECODE_DISABLED
	if (!v9p->fpu_on) {
		v9p->post_precise_trap(sp, Sparcv9_trap_fp_disabled);
		return;
	}
#endif /* FP_DECODE_DISABLED */
	FIXME_WARNING(("non-native implementation of fmovs (sparcv9_fmovs) not yet completed")); exit(0);
	ENDI

#endif	/* } */





	/*
	 * Instruction: sparcv9_fmovd
	 */

#if !defined(HAS_NATIVE_sparcv9_fmovd)	/* { */

IMPL(fmovd)
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
#ifndef FP_DECODE_DISABLED
	if (!v9p->fpu_on) {
		v9p->post_precise_trap(sp, Sparcv9_trap_fp_disabled);
		return;
	}
#endif /* FP_DECODE_DISABLED */
	FIXME_WARNING(("non-native implementation of fmovd (sparcv9_fmovd) not yet completed")); exit(0);
	ENDI

#endif	/* } */





	/*
	 * Instruction: sparcv9_fmovq
	 */

#if !defined(HAS_NATIVE_sparcv9_fmovq)	/* { */

IMPL(fmovq)
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
#ifndef FP_DECODE_DISABLED
	if (!v9p->fpu_on) {
		v9p->post_precise_trap(sp, Sparcv9_trap_fp_disabled);
		return;
	}
#endif /* FP_DECODE_DISABLED */
	FIXME_WARNING(("non-native implementation of fmovq (sparcv9_fmovq) not yet completed")); exit(0);
	ENDI

#endif	/* } */



IMPL( fmovscc )
	int ccr;
	FP_EXEC_FPU_ON_CHECK;
	ccr = sp->v9_ccr;
	if (MOVCC_cc) ccr>>=4;

	if ( (sparcv9_cc_magic[MOVCC_cond] >> (ccr & 0xf)) &1 ) {
		F32dest = F32src1;
	}
	NEXT_INSTN(sp);
	ENDDEF



IMPL( fmovsfcc )
	int ccr;
	FP_EXEC_FPU_ON_CHECK;
	if (MOVCC_cc == 0)
		ccr = V9_FSR_FCC0(sp->v9_fsr_ctrl);
	else
		ccr = V9_FSR_FCCN(sp->v9_fsr_ctrl, MOVCC_cc);

	if ( (sparcv9_fcc_magic[MOVCC_cond] >> ccr) & 1 ) {
		F32dest = F32src1;
	}
	NEXT_INSTN(sp);
	ENDDEF



IMPL( fmovdcc )
	int ccr;
	FP_EXEC_FPU_ON_CHECK;
	ccr = sp->v9_ccr;
	if (MOVCC_cc) ccr>>=4;

	if ( (sparcv9_cc_magic[MOVCC_cond] >> (ccr & 0xf)) &1 ) {
		F64dest = F64src1;
	}
	NEXT_INSTN(sp);
	ENDDEF

IMPL( fmovrs_z )
	FP_EXEC_FPU_ON_CHECK;
	if (SRsrc1 == 0)
		F32dest = F32src2;
	ENDI
IMPL( fmovrs_lez )
	FP_EXEC_FPU_ON_CHECK;
	if (SRsrc1 <= 0)
		F32dest = F32src2;
	ENDI
IMPL( fmovrs_lz )
	FP_EXEC_FPU_ON_CHECK;
	if (SRsrc1 < 0)
		F32dest = F32src2;
	ENDI
IMPL( fmovrs_nz )
	FP_EXEC_FPU_ON_CHECK;
	if (SRsrc1 != 0)
		F32dest = F32src2;
	ENDI
IMPL( fmovrs_gz )
	FP_EXEC_FPU_ON_CHECK;
	if (SRsrc1 > 0)
		F32dest = F32src2;
	ENDI
IMPL( fmovrs_gez )
	FP_EXEC_FPU_ON_CHECK;
	if (SRsrc1 >= 0)
		F32dest = F32src2;
	ENDI

IMPL( fmovrd_z )
	FP_EXEC_FPU_ON_CHECK;
	if (SRsrc1 == 0)
		F64dest = F64src2;
	ENDI
IMPL( fmovrd_lez )
	FP_EXEC_FPU_ON_CHECK;
	if (SRsrc1 <= 0)
		F64dest = F64src2;
	ENDI
IMPL( fmovrd_lz )
	FP_EXEC_FPU_ON_CHECK;
	if (SRsrc1 < 0)
		F64dest = F64src2;
	ENDI
IMPL( fmovrd_nz )
	FP_EXEC_FPU_ON_CHECK;
	if (SRsrc1 != 0)
		F64dest = F64src2;
	ENDI
IMPL( fmovrd_gz )
	FP_EXEC_FPU_ON_CHECK;
	if (SRsrc1 > 0)
		F64dest = F64src2;
	ENDI
IMPL( fmovrd_gez )
	FP_EXEC_FPU_ON_CHECK;
	if (SRsrc1 >= 0)
		F64dest = F64src2;
	ENDI



IMPL( fmovdfcc )
	int ccr;
	FP_EXEC_FPU_ON_CHECK;
	if (MOVCC_cc == 0)
		ccr = V9_FSR_FCC0(sp->v9_fsr_ctrl);
	else
		ccr = V9_FSR_FCCN(sp->v9_fsr_ctrl, MOVCC_cc);

	if ( (sparcv9_fcc_magic[MOVCC_cond] >> ccr) & 1 ) {
		F64dest = F64src1;
	}
	NEXT_INSTN(sp);
	ENDDEF





	/*
	 * Instruction: sparcv9_fnegs
	 */

#if !defined(HAS_NATIVE_sparcv9_fnegs)	/* { */

IMPL(fnegs)
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
#ifndef FP_DECODE_DISABLED
	if (!v9p->fpu_on) {
		v9p->post_precise_trap(sp, Sparcv9_trap_fp_disabled);
		return;
	}
#endif /* FP_DECODE_DISABLED */
	FIXME_WARNING(("non-native implementation of fnegs (sparcv9_fnegs) not yet completed")); exit(0);
	ENDI

#endif	/* } */





	/*
	 * Instruction: sparcv9_fnegd
	 */

#if !defined(HAS_NATIVE_sparcv9_fnegd)	/* { */

IMPL(fnegd)
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
#ifndef FP_DECODE_DISABLED
	if (!v9p->fpu_on) {
		v9p->post_precise_trap(sp, Sparcv9_trap_fp_disabled);
		return;
	}
#endif /* FP_DECODE_DISABLED */
	FIXME_WARNING(("non-native implementation of fnegd (sparcv9_fnegd) not yet completed")); exit(0);
	ENDI

#endif	/* } */





	/*
	 * Instruction: sparcv9_fnegq
	 */

#if !defined(HAS_NATIVE_sparcv9_fnegq)	/* { */

IMPL(fnegq)
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
#ifndef FP_DECODE_DISABLED
	if (!v9p->fpu_on) {
		v9p->post_precise_trap(sp, Sparcv9_trap_fp_disabled);
		return;
	}
#endif /* FP_DECODE_DISABLED */
	FIXME_WARNING(("non-native implementation of fnegq (sparcv9_fnegq) not yet completed")); exit(0);
	ENDI

#endif	/* } */





	/*
	 * Instruction: sparcv9_fabss
	 */

#if !defined(HAS_NATIVE_sparcv9_fabss)	/* { */

IMPL(fabss)
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
#ifndef FP_DECODE_DISABLED
	if (!v9p->fpu_on) {
		v9p->post_precise_trap(sp, Sparcv9_trap_fp_disabled);
		return;
	}
#endif /* FP_DECODE_DISABLED */
	FIXME_WARNING(("non-native implementation of fabss (sparcv9_fabss) not yet completed")); exit(0);
	ENDI

#endif	/* } */





	/*
	 * Instruction: sparcv9_fabsd
	 */

#if !defined(HAS_NATIVE_sparcv9_fabsd)	/* { */

IMPL(fabsd)
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
#ifndef FP_DECODE_DISABLED
	if (!v9p->fpu_on) {
		v9p->post_precise_trap(sp, Sparcv9_trap_fp_disabled);
		return;
	}
#endif /* FP_DECODE_DISABLED */
	FIXME_WARNING(("non-native implementation of fabsd (sparcv9_fabsd) not yet completed")); exit(0);
	ENDI

#endif	/* } */





	/*
	 * Instruction: sparcv9_fabsq
	 */

#if !defined(HAS_NATIVE_sparcv9_fabsq)	/* { */

IMPL(fabsq)
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
#ifndef FP_DECODE_DISABLED
	if (!v9p->fpu_on) {
		v9p->post_precise_trap(sp, Sparcv9_trap_fp_disabled);
		return;
	}
#endif /* FP_DECODE_DISABLED */
	FIXME_WARNING(("non-native implementation of fabsq (sparcv9_fabsq) not yet completed")); exit(0);
	ENDI

#endif	/* } */



	/*
	 * Instruction: sparcv9_fstoi
	 */

#if !defined(HAS_NATIVE_sparcv9_fstoi)	/* { */

IMPL(fstoi)
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
#ifndef FP_DECODE_DISABLED
	if (!v9p->fpu_on) {
		v9p->post_precise_trap(sp, Sparcv9_trap_fp_disabled);
		return;
	}
#endif /* FP_DECODE_DISABLED */
	FIXME_WARNING(("non-native implementation of fstoi (sparcv9_fstoi) not yet completed")); exit(0);
	ENDI

#endif	/* } */


	/*
	 * Instruction: sparcv9_fitos
	 */

#if !defined(HAS_NATIVE_sparcv9_fitos)	/* { */

IMPL(fitos)
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
#ifndef FP_DECODE_DISABLED
	if (!v9p->fpu_on) {
		v9p->post_precise_trap(sp, Sparcv9_trap_fp_disabled);
		return;
	}
#endif /* FP_DECODE_DISABLED */
	FIXME_WARNING(("non-native implementation of fitos (sparcv9_fitos) not yet completed")); exit(0);
	ENDI

#endif	/* } */



	/*
	 * Instruction: sparcv9_fdtoi
	 */

#if !defined(HAS_NATIVE_sparcv9_fdtoi)	/* { */

IMPL(fdtoi)
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
#ifndef FP_DECODE_DISABLED
	if (!v9p->fpu_on) {
		v9p->post_precise_trap(sp, Sparcv9_trap_fp_disabled);
		return;
	}
#endif /* FP_DECODE_DISABLED */
	FIXME_WARNING(("non-native implementation of fdtoi (sparcv9_fdtoi) not yet completed")); exit(0);
	ENDI

#endif	/* } */



	/*
	 * Instruction: sparcv9_fitod
	 */

#if !defined(HAS_NATIVE_sparcv9_fitod)	/* { */

IMPL(fitod)
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
#ifndef FP_DECODE_DISABLED
	if (!v9p->fpu_on) {
		v9p->post_precise_trap(sp, Sparcv9_trap_fp_disabled);
		return;
	}
#endif /* FP_DECODE_DISABLED */
	FIXME_WARNING(("non-native implementation of fitod (sparcv9_fitod) not yet completed")); exit(0);
	ENDI

#endif	/* } */



	/*
	 * Instruction: sparcv9_fstox
	 */

#if !defined(HAS_NATIVE_sparcv9_fstox)	/* { */

IMPL(fstox)
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
#ifndef FP_DECODE_DISABLED
	if (!v9p->fpu_on) {
		v9p->post_precise_trap(sp, Sparcv9_trap_fp_disabled);
		return;
	}
#endif /* FP_DECODE_DISABLED */
	FIXME_WARNING(("non-native implementation of fstox (sparcv9_fstox) not yet completed")); exit(0);
	ENDI

#endif	/* } */



	/*
	 * Instruction: sparcv9_fxtos
	 */

#if !defined(HAS_NATIVE_sparcv9_fxtos)	/* { */

IMPL(fxtos)
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
#ifndef FP_DECODE_DISABLED
	if (!v9p->fpu_on) {
		v9p->post_precise_trap(sp, Sparcv9_trap_fp_disabled);
		return;
	}
#endif /* FP_DECODE_DISABLED */
	FIXME_WARNING(("non-native implementation of fxtos (sparcv9_fxtos) not yet completed")); exit(0);
	ENDI

#endif	/* } */


	/*
	 * Instruction: sparcv9_fdtox
	 */

#if !defined(HAS_NATIVE_sparcv9_fdtox)	/* { */

IMPL(fdtox)
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
#ifndef FP_DECODE_DISABLED
	if (!v9p->fpu_on) {
		v9p->post_precise_trap(sp, Sparcv9_trap_fp_disabled);
		return;
	}
#endif /* FP_DECODE_DISABLED */
	FIXME_WARNING(("non-native implementation of fdtox (sparcv9_fdtox) not yet completed")); exit(0);
	ENDI

#endif	/* } */



	/*
	 * Instruction: sparcv9_fxtod
	 */

#if !defined(HAS_NATIVE_sparcv9_fxtod)	/* { */

IMPL(fxtod)
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
#ifndef FP_DECODE_DISABLED
	if (!v9p->fpu_on) {
		v9p->post_precise_trap(sp, Sparcv9_trap_fp_disabled);
		return;
	}
#endif /* FP_DECODE_DISABLED */
	FIXME_WARNING(("non-native implementation of fxtod (sparcv9_fxtod) not yet completed")); exit(0);
	ENDI

#endif	/* } */


	/*
	 * Instruction: sparcv9_fzerod
	 */

#if !defined(HAS_NATIVE_sparcv9_fzerod)	/* { */

IMPL(fzerod)
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
#ifndef FP_DECODE_DISABLED
	if (!v9p->fpu_on) {
		v9p->post_precise_trap(sp, Sparcv9_trap_fp_disabled);
		return;
	}
#endif /* FP_DECODE_DISABLED */
	FIXME_WARNING(("non-native implementation of fzero (sparcv9_fzerod) not yet completed")); exit(0);
	ENDI

#endif	/* } */



#if !defined(HAS_NATIVE_sparcv9_fzeros)	/* { */

IMPL(fzeros)
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
#ifndef FP_DECODE_DISABLED
	if (!v9p->fpu_on) {
		v9p->post_precise_trap(sp, Sparcv9_trap_fp_disabled);
		return;
	}
#endif /* FP_DECODE_DISABLED */
	FIXME_WARNING(("non-native implementation of fzeros (sparcv9_fzeros) not yet completed")); exit(0);
	ENDI

#endif	/* } */


#if !defined(HAS_NATIVE_sparcv9_foned)	/* { */

IMPL(foned)
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
#ifndef FP_DECODE_DISABLED
	if (!v9p->fpu_on) {
		v9p->post_precise_trap(sp, Sparcv9_trap_fp_disabled);
		return;
	}
#endif /* FP_DECODE_DISABLED */
	FIXME_WARNING(("non-native implementation of foned (sparcv9_foned) not yet completed")); exit(0);
	ENDI

#endif	/* } */


#if !defined(HAS_NATIVE_sparcv9_fzerod)	/* { */

IMPL(fones)
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
#ifndef FP_DECODE_DISABLED
	if (!v9p->fpu_on) {
		v9p->post_precise_trap(sp, Sparcv9_trap_fp_disabled);
		return;
	}
#endif /* FP_DECODE_DISABLED */
	FIXME_WARNING(("non-native implementation of fone (sparcv9_fones) not yet completed")); exit(0);
	ENDI

#endif	/* } */








/* ------------------------------------------------------------ */


	/*
	 * Basic branch instructions
	 */


			/* Note: special case - normally taken branches */
			/* always execute their delay slots - not the always case ! */

IMPL( bralways_ds_annul )	/* branch always annul delay slot */
	tvaddr_t xpc;

	xpc = Rpc + SBRoffset32;
	Rpc = xpc;
	Rnpc = xpc + 4;
	ENDDEF


IMPL( bralways_ds )		/* branch always executing delay slot */
	tvaddr_t xpc;

	xpc = Rpc + SBRoffset32;
	Rpc = Rnpc;
	Rnpc = xpc;
	ENDDEF

IMPL( brnever_ds_annul )	/* branch never, but annul delay slot */
	tvaddr_t xpc;

	xpc = Rnpc + 4;
	Rpc = xpc;
	Rnpc = xpc + 4;
	ENDDEF




/* ------------------------------------------------------------ */


	/*
	 * Call instruction + Jump and links ...
	 */

IMPL( call )
	tvaddr_t tpc, opc;
	sparcv9_cpu_t * v9p;

	v9p = (sparcv9_cpu_t *)(sp->specificp);

	opc = Rpc;
	tpc = opc + (sint64_t)Simm32;
	tpc &= ~0x3;
	Rpc = Rnpc;
	Rnpc = tpc;

	if (v9p->pstate.addr_mask) opc &= MASK64(31,0);

	IReg( Reg_sparcv9_o7 ) = opc;
	ENDDEF




IMPL( jmpl_imm )
	tvaddr_t opc;
	sparcv9_cpu_t * v9p;

	v9p = (sparcv9_cpu_t *)(sp->specificp);

	opc = Rpc;	/* stash incase Rdest is same reg as Rsrc */
	Rpc = Rnpc;
	Rnpc = Rsrc1 + Simm16;
	Rnpc &= ~0x3;

	if (v9p->pstate.addr_mask) opc &= MASK64(31,0);

	Rdest = opc;
	ENDDEF
	

IMPL( jmpl_imm_rd0 )	/* fast track normal return-from-call instructions */
	Rpc = Rnpc;
	Rnpc = Rsrc1 + Simm16;
	Rnpc &= ~0x3;
	ENDDEF
	
IMPL( jmpl_rrr )
	tvaddr_t opc;
	sparcv9_cpu_t * v9p;

	v9p = (sparcv9_cpu_t *)(sp->specificp);

	opc = Rpc;	/* stash incase Rdest is same reg as Rsrc */
	Rpc = Rnpc;
	Rnpc = Rsrc1 + Rsrc2;
	Rnpc &= ~0x3;

	if (v9p->pstate.addr_mask) opc &= MASK64(31,0);

	Rdest = opc;
	ENDDEF
	

IMPL( jmpl_rrr_rd0 )	/* fast track normal return-from-call instructions */
	Rpc = Rnpc;
	Rnpc = Rsrc1 + Rsrc2;
	Rnpc &= ~0x3;
	ENDDEF
	







/* ------------------------------------------------------------ */

	/*
	 * Specialist maths instructions
	 */

IMPL( udiv64_imm )
	sparcv9_udiv64( sp, Rdest_num, Rsrc1, Simm16 );
	ENDDEF

IMPL( udiv64_rrr )
	sparcv9_udiv64( sp, Rdest_num, Rsrc1, Rsrc2 );
	ENDDEF

IMPL(sdiv64_imm)
	if (Simm16 == 0) {
		sparcv9_cpu_t * v9p = (sparcv9_cpu_t *)(sp->specificp);
		v9p->post_precise_trap(sp, Sparcv9_trap_division_by_zero);
		return;	
	}
	if (!Zero_Reg(Rdest_num)) {
		Rdest = (int64_t)Rsrc1 / (int64_t)Simm16;
	}
	ENDI

IMPL(sdiv64_rrr)
	if (Rsrc2 == 0) {
		sparcv9_cpu_t * v9p = (sparcv9_cpu_t *)(sp->specificp);
		v9p->post_precise_trap(sp, Sparcv9_trap_division_by_zero);
		return;	
	}
	if (!Zero_Reg(Rdest_num)) {
		Rdest = (int64_t)Rsrc1 / (int64_t)Rsrc2;
	}
	ENDI

IMPL(sdiv_imm)
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
	int64_t foo;
	if (Simm16 == 0) {
		v9p->post_precise_trap(sp, Sparcv9_trap_division_by_zero);
		return;
	}
	if (!Zero_Reg(Rdest_num)) {
		foo = (((int64_t)sp->v9_y) << 32) | (uint32_t)Rsrc1;
		foo = foo / (int32_t)Simm16;
		if (foo >= (1ul << 31))
			foo = (1ul << 31) - 1;
		else if (foo <= (int64_t)0xffffffff7fffffffUL)
			foo = 0x80000000L;
		Rdest = (int32_t)foo;
	}
	ENDI

IMPL(udiv_imm)
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
	uint64_t foo;
	if (Simm16 == 0) {
		v9p->post_precise_trap(sp, Sparcv9_trap_division_by_zero);
		return;
	}
	if (!Zero_Reg(Rdest_num)) {
		foo = (((int64_t)sp->v9_y) << 32) | (uint32_t)Rsrc1;
		foo = ((uint64_t)foo) / ((uint32_t)(int32_t)Simm16);
		if (foo >= (1ull << 32))
			foo = (1ull << 32) - 1;
		Rdest = (uint32_t)foo;
	}
	ENDI

IMPL(sdiv_rrr)
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
	int64_t foo;
	if ((int32_t)Rsrc2 == 0) {
		v9p->post_precise_trap(sp, Sparcv9_trap_division_by_zero);
		return;
	}
	if (!Zero_Reg(Rdest_num)) {
		foo = (((int64_t)sp->v9_y) << 32) | (uint32_t)Rsrc1;
		foo = foo / (int32_t)Rsrc2;
		if (foo >= (1ul << 31))
			foo = (1ul << 31) - 1;
		else if (foo <= (int64_t)0xffffffff7fffffffUL)
			foo = 0x80000000L;
		Rdest = (int32_t)foo;
	}
	ENDI

IMPL(udiv_rrr)
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
	uint64_t foo;
	if ((int32_t)Rsrc2 == 0) {
		v9p->post_precise_trap(sp, Sparcv9_trap_division_by_zero);
		return;
	}
	if (!Zero_Reg(Rdest_num)) {
		foo = (((int64_t)sp->v9_y) << 32) | (uint32_t)Rsrc1;
		foo = (int64_t)foo / (uint32_t)Rsrc2;
		if (foo >= (1ull << 32))
			foo = (1ull << 32) - 1;
		Rdest = (uint32_t)foo;
	}
	ENDI

IMPL(sdiv_cc_imm)
	sparcv9_cpu_t *v9p = (sparcv9_cpu_t*)(sp->specificp);
	int64_t foo;
	int v = 0;
	if (Simm16 == 0) {
		v9p->post_precise_trap(sp, Sparcv9_trap_division_by_zero);
		return;
	}
	foo = (((int64_t)sp->v9_y) << 32) | (uint32_t)Rsrc1;
	foo = foo / (int32_t)Simm16;
	if (foo >= (1l << 31)) {
		foo = (1l << 31) - 1;
		v = (1 << 1); /* icc.v */
	} else if (foo <= (int64_t)0xffffffff7fffffffUL) {
		foo = 0x80000000L;
		v = (1 << 1); /* icc.v */
	}
	foo = (int32_t)foo;
	sp->v9_ccr = ((foo & (1ul << 31)) ? (1 << 3) : 0) | /* icc.n */
		(((uint32_t)foo == 0) ? (1 << 2) : 0) | /* icc.z */
		((foo & (1ul << 63)) ? (1 << 7) : 0) | /* xcc.n */
		((foo == 0) ? (1 << 6) : 0) | /* xcc.z */
		v;
	if (!Zero_Reg(Rdest_num))
		Rdest = foo;
	ENDI

IMPL(udiv_cc_imm)
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
	uint64_t foo;
	int v = 0;
	if (Simm16 == 0) {
		v9p->post_precise_trap(sp, Sparcv9_trap_division_by_zero);
		return;
	}
	foo = (((int64_t)sp->v9_y) << 32) | (uint32_t)Rsrc1;
	foo = ((uint64_t)foo) / ((uint32_t)(int32_t)Simm16);
	if (foo >= (1ul << 32)) {
		foo = (1ul << 32) - 1;
		v = (1 << 1); /* icc.v */
	}
	foo = (uint32_t)foo;
	sp->v9_ccr = ((foo & (1ul << 31)) ? (1 << 3) : 0) | /* icc.n */
		(((uint32_t)foo == 0) ? (1 << 2) : 0) | /* icc.z */
		((foo & (1ul << 63)) ? (1 << 7) : 0) | /* xcc.n */
		((foo == 0) ? (1 << 6) : 0) | /* xcc.z */
		v;
	if (!Zero_Reg(Rdest_num))
		Rdest = foo;
	ENDI

IMPL(sdiv_cc_rrr)
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
	int64_t foo;
	int v = 0;
	if ((int32_t)Rsrc2 == 0) {
		v9p->post_precise_trap(sp, Sparcv9_trap_division_by_zero);
		return;
	}
	foo = (((int64_t)sp->v9_y) << 32) | (uint32_t)Rsrc1;
	foo = foo / (int32_t)Rsrc2;
	if (foo >= (1l << 31)) {
		foo = (1l << 31) - 1;
		v = (1 << 1); /* icc.v */
	} else if (foo <= (int64_t)0xffffffff7fffffffUL) {
		foo = 0x80000000L;
		v = (1 << 1); /* icc.v */
	}
	foo = (int32_t)foo;
	sp->v9_ccr = ((foo & (1ul << 31)) ? (1 << 3) : 0) | /* icc.n */
		(((uint32_t)foo == 0) ? (1 << 2) : 0) | /* icc.z */
		((foo & (1ul << 63)) ? (1 << 7) : 0) | /* xcc.n */
		((foo == 0) ? (1 << 6) : 0) | /* xcc.z */
		v;
	if (!Zero_Reg(Rdest_num))
		Rdest = foo;
	ENDI

IMPL(udiv_cc_rrr)
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
	uint64_t foo;
	int v = 0;
	if ((int32_t)Rsrc2 == 0) {
		v9p->post_precise_trap(sp, Sparcv9_trap_division_by_zero);
		return;
	}
	foo = (((int64_t)sp->v9_y) << 32) | (uint32_t)Rsrc1;
	foo = ((int64_t)foo) / ((uint32_t)Rsrc2);
	if (foo >= (1ull << 32)) {
		foo = (1ull << 32) - 1;
		v = (1 << 1); /* icc.v */
	}
	foo = (uint32_t)foo;
	sp->v9_ccr = ((foo & (1ul << 31)) ? (1 << 3) : 0) | /* icc.n */
		(((uint32_t)foo == 0) ? (1 << 2) : 0) | /* icc.z */
		((foo & (1ul << 63)) ? (1 << 7) : 0) | /* xcc.n */
		((foo == 0) ? (1 << 6) : 0) | /* xcc.z */
		v;
	if (!Zero_Reg(Rdest_num))
		Rdest = foo;
	ENDI

IMPL(smul_imm)
	uint64_t foo;
	foo = (int64_t)(int32_t)Rsrc1 * (int64_t)(int32_t)Simm16;
	sp->v9_y = foo >> 32;
	if (!Zero_Reg(Rdest_num))
		Rdest = foo;
	ENDI

IMPL(umul_imm)
	uint64_t foo;
	foo = (uint64_t)(uint32_t)Rsrc1 * (uint64_t)(uint32_t)(int32_t)Simm16;
	sp->v9_y = foo >> 32;
	if (!Zero_Reg(Rdest_num))
		Rdest = foo;
	ENDI

IMPL(smul_cc_imm)
	uint64_t foo;
	foo = (int64_t)(int32_t)Rsrc1 * (int64_t)(int32_t)Simm16;
	sp->v9_y = foo >> 32;
	sp->v9_ccr = ((foo & (1ul << 31)) ? (1 << 3) : 0) | /* icc.n */
		(((uint32_t)foo == 0) ? (1 << 2) : 0) | /* icc.z */
		((foo & (1ul << 63)) ? (1 << 7) : 0) | /* xcc.n */
		((foo == 0) ? (1 << 6) : 0); /* xcc.z */
	if (!Zero_Reg(Rdest_num))
		Rdest = foo;
	ENDI

IMPL(umul_cc_imm)
	uint64_t foo;
	foo = (uint64_t)(uint32_t)Rsrc1 * (uint64_t)(uint32_t)(int32_t)Simm16;
	sp->v9_y = foo >> 32;
	sp->v9_ccr = ((foo & (1ul << 31)) ? (1 << 3) : 0) | /* icc.n */
		(((uint32_t)foo == 0) ? (1 << 2) : 0) | /* icc.z */
		((foo & (1ul << 63)) ? (1 << 7) : 0) | /* xcc.n */
		((foo == 0) ? (1 << 6) : 0); /* xcc.z */
	if (!Zero_Reg(Rdest_num))
		Rdest = foo;
	ENDI

IMPL(mulscc_rrr)
	uint64_t foo;
	uint32_t s1, s2;
	uint32_t d;
	uint32_t v, c;
	foo = (((int64_t)Rsrc1) << 32) | (uint32_t)sp->v9_y;
	/* icc.n xor icc.v */
	s1 = ((sp->v9_ccr >> 3) & 1) ^ ((sp->v9_ccr >> 1) & 1);
	s1 = (s1 << 31) | (((uint32_t)Rsrc1) >> 1);
	if (foo & 1)
		s2 = (uint32_t)Rsrc2;
	else
		s2 = 0;
	foo >>= 1;
	sp->v9_y = (uint32_t)foo;
	d = s1 + s2;
	v = (s1 & s2 & ~d) | (~s1 & ~s2 & d);
	c = (s1 & s2) | (~d & (s1 | s2));
	sp->v9_ccr = (sp->v9_ccr & V9_xcc_mask);
	sp->v9_ccr |= V9_icc_v((v >> 31) & 1);
	sp->v9_ccr |= V9_icc_c((c >> 31) & 1);
	sp->v9_ccr |= V9_icc_n((d >> 31) & 1);
	sp->v9_ccr |= V9_icc_z((d & MASK64(31,0)) ? 0 : 1);
	if (!Zero_Reg(Rdest_num))
		Rdest = (uint32_t)d;
	ENDI

IMPL(mulscc_imm)
	uint64_t foo;
	uint32_t s1, s2;
	uint32_t d;
	uint32_t v, c;
	foo = (((int64_t)Rsrc1) << 32) | (uint32_t)sp->v9_y;
	/* icc.n xor icc.v */
	s1 = ((sp->v9_ccr >> 3) & 1) ^ ((sp->v9_ccr >> 1) & 1);
	s1 = (s1 << 31) | (((uint32_t)Rsrc1) >> 1);
	if (foo & 1)
		s2 = (uint32_t)Simm16;
	else
		s2 = 0;
	foo >>= 1;
	sp->v9_y = (uint32_t)foo;
	d = s1 + s2;
	v = (s1 & s2 & ~d) | (~s1 & ~s2 & d);
	c = (s1 & s2) | (~d & (s1 | s2));
	sp->v9_ccr = (sp->v9_ccr & V9_xcc_mask);
	sp->v9_ccr |= V9_icc_v((v >> 31) & 1);
	sp->v9_ccr |= V9_icc_c((c >> 31) & 1);
	sp->v9_ccr |= V9_icc_n((d >> 31) & 1);
	sp->v9_ccr |= V9_icc_z((d & MASK64(31,0)) ? 0 : 1);
	if (!Zero_Reg(Rdest_num))
		Rdest = (uint32_t)d;
	ENDI

IMPL(smul_rrr)
	uint64_t foo;
	foo = (int64_t)(int32_t)Rsrc1 * (int64_t)(int32_t)Rsrc2;
	sp->v9_y = foo >> 32;
	if (!Zero_Reg(Rdest_num))
		Rdest = foo;
	ENDI


IMPL(umul_rrr)
	uint64_t foo;
	foo = (uint64_t)(uint32_t)Rsrc1 * (uint64_t)(uint32_t)Rsrc2;
	sp->v9_y = foo >> 32;
	if (!Zero_Reg(Rdest_num))
		Rdest = foo;
	ENDI

IMPL(smul_cc_rrr)
	uint64_t foo;
	foo = (int64_t)(int32_t)Rsrc1 * (int64_t)(int32_t)Rsrc2;
	sp->v9_y = foo >> 32;
	sp->v9_ccr = ((foo & (1ul << 31)) ? (1 << 3) : 0) | /* icc.n */
		(((uint32_t)foo == 0) ? (1 << 2) : 0) | /* icc.z */
		((foo & (1ul << 63)) ? (1 << 7) : 0) | /* xcc.n */
		((foo == 0) ? (1 << 6) : 0); /* xcc.z */
	if (!Zero_Reg(Rdest_num))
		Rdest = foo;
	ENDI

IMPL(umul_cc_rrr)
	uint64_t foo;
	foo = (uint64_t)(uint32_t)Rsrc1 * (uint64_t)(uint32_t)Rsrc2;
	sp->v9_y = foo >> 32;
	sp->v9_ccr = ((foo & (1ul << 31)) ? (1 << 3) : 0) | /* icc.n */
		(((uint32_t)foo == 0) ? (1 << 2) : 0) | /* icc.z */
		((foo & (1ul << 63)) ? (1 << 7) : 0) | /* xcc.n */
		((foo == 0) ? (1 << 6) : 0); /* xcc.z */
	if (!Zero_Reg(Rdest_num))
		Rdest = foo;
	ENDI


/* ------------------------------------------------------------ */

	/*
	 * trap instructions
	 */


IMPL( trap_imm_fast )
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
	int tn = Simm16;

	if (V9_User==v9p->state)
		tn &= 0x7f;
	else
		tn &= 0xff;

	if (SS_MAGIC_TRAP_CC(TRAP_cc) && SS_MAGIC_TRAP(sp, tn)) {
		NEXT_INSTN(sp);
		return;
	}

	v9p->post_precise_trap(sp, tn+Sparcv9_trap_trap_instruction);
	ENDDEF


IMPL( trapcc_imm )
	sparcv9_trapcc( sp, Rsrc1 + Simm16, TRAP_cc, TRAP_cond );
	ENDDEF


IMPL( trapcc_rr )
	sparcv9_trapcc( sp, Rsrc1 + Rsrc2, TRAP_cc, TRAP_cond );
	ENDDEF


/* ------------------------------------------------------------ */

IMPL( movcc_imm )
	int ccr;
	ccr = sp->v9_ccr;
	if (MOVCC_cc) ccr>>=4;

	if ( (sparcv9_cc_magic[MOVCC_cond] >> (ccr & 0xf)) &1 ) {
		Rdest = Simm16;
	}
	NEXT_INSTN(sp);
	ENDDEF



IMPL( movcc_rr )
	int ccr;
	ccr = sp->v9_ccr;
	if (MOVCC_cc) ccr>>=4;

	if ( (sparcv9_cc_magic[MOVCC_cond] >> (ccr & 0xf)) &1 ) {
		Rdest = Rsrc2;
	}
	NEXT_INSTN(sp);
	ENDDEF



IMPL( movfcc_imm )
	int ccr;
	FP_EXEC_FPU_ON_CHECK;
	if (MOVCC_cc == 0)
		ccr = V9_FSR_FCC0(sp->v9_fsr_ctrl);
	else
		ccr = V9_FSR_FCCN(sp->v9_fsr_ctrl, MOVCC_cc);

	if ( (sparcv9_fcc_magic[MOVCC_cond] >> ccr) & 1 ) {
		Rdest = Simm16;
	}
	NEXT_INSTN(sp);
	ENDDEF



IMPL( movfcc_rr )
	int ccr;
	FP_EXEC_FPU_ON_CHECK;
	if (MOVCC_cc == 0)
		ccr = V9_FSR_FCC0(sp->v9_fsr_ctrl);
	else
		ccr = V9_FSR_FCCN(sp->v9_fsr_ctrl, MOVCC_cc);

	if ( (sparcv9_fcc_magic[MOVCC_cond] >> ccr) & 1 ) {
		Rdest = Rsrc2;
	}
	NEXT_INSTN(sp);
	ENDDEF


IMPL( movr_imm_z )
	if (Rsrc1 == 0)
		Rdest = Simm16;
	ENDI
IMPL( movr_imm_lez )
	if (SRsrc1 <= 0)
		Rdest = Simm16;
	ENDI
IMPL( movr_imm_lz )
	if (SRsrc1 < 0)
		Rdest = Simm16;
	ENDI
IMPL( movr_imm_nz )
	if (SRsrc1 != 0)
		Rdest = Simm16;
	ENDI
IMPL( movr_imm_gz )
	if (SRsrc1 > 0)
		Rdest = Simm16;
	ENDI
IMPL( movr_imm_gez )
	if (SRsrc1 >= 0)
		Rdest = Simm16;
	ENDI
IMPL( movr_rr_z )
	if (Rsrc1 == 0)
		Rdest = Rsrc2;
	ENDI
IMPL( movr_rr_lez )
	if (SRsrc1 <= 0)
		Rdest = Rsrc2;
	ENDI
IMPL( movr_rr_lz )
	if (SRsrc1 < 0)
		Rdest = Rsrc2;
	ENDI
IMPL( movr_rr_nz )
	if (SRsrc1 != 0)
		Rdest = Rsrc2;
	ENDI
IMPL( movr_rr_gz )
	if (SRsrc1 > 0)
		Rdest = Rsrc2;
	ENDI
IMPL( movr_rr_gez )
	if (SRsrc1 >= 0)
		Rdest = Rsrc2;
	ENDI

IMPL( popc_imm )
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
	int64_t cnt;
	int64_t val;

	if (Rsrc1_num != 0) {
		v9p->post_precise_trap(sp, Sparcv9_trap_illegal_instruction);
		return; 
	}
	if (!Zero_Reg(Rdest_num)) {
		val = (int64_t)(int32_t)Simm16;
		for (cnt = 0; val != 0; val &= val-1)
			cnt++;
		Rdest = cnt;
	}
	ENDI

IMPL( popc_rrr )
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
	int64_t cnt;
	uint64_t val;

	if (Rsrc1_num != 0) {
		v9p->post_precise_trap(sp, Sparcv9_trap_illegal_instruction);
		return; 
	}
	if (!Zero_Reg(Rdest_num)) {
		val = Rsrc2;
		for (cnt = 0; val != 0; val &= val-1)
			cnt++;
		Rdest = cnt;
	}
	ENDI


/* ------------------------------------------------------------ */

	/*
	 * Specialist instructions ...
	 * ... typically implementation dependent
	 * ... so use the provided callbacks to the actual device
	 */

IMPL( read_state_reg )
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
	v9p->read_state_reg( sp, Rdest_num, Rsrc1_num );
	ENDDEF
	
IMPL( write_state_reg_imm )
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
	v9p->write_state_reg( sp, Rdest_num, Rsrc1 ^ Simm16 );
	ENDDEF

IMPL( write_state_reg_rrr )
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
	v9p->write_state_reg( sp, Rdest_num, Rsrc1 ^ Rsrc2 );
	ENDDEF


IMPL( read_priv_reg )
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
	v9p->read_priv_reg( sp, Rdest_num, Rsrc1_num );
	ENDDEF

IMPL( write_priv_reg_imm )
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
	v9p->write_priv_reg( sp, Rdest_num, Rsrc1 ^ Simm16 );
	ENDDEF

IMPL( write_priv_reg_rrr )
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
	v9p->write_priv_reg( sp, Rdest_num, Rsrc1 ^ Rsrc2 );
	ENDDEF


IMPL( read_hyper_priv_reg )
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
	v9p->read_hyp_priv_reg( sp, Rdest_num, Rsrc1_num );
	ENDDEF

IMPL( write_hyper_priv_reg_imm )
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
	v9p->write_hyp_priv_reg( sp, Rdest_num, Rsrc1 ^ Simm16 );
	ENDDEF

IMPL( write_hyper_priv_reg_rrr )
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
	v9p->write_hyp_priv_reg( sp, Rdest_num, Rsrc1 ^ Rsrc2 );
	ENDDEF


IMPL( stbar )
	/* Nothing to do in legion?? */
	NEXT_INSTN(sp);
	ENDDEF

IMPL( membar )
	/* Nothing to do in legion?? */
	NEXT_INSTN(sp);
	ENDDEF



IMPL( save_imm )
	sparcv9_save_instr(sp, Rdest_num, Rsrc1 + Simm16);
	ENDDEF

IMPL( save_rrr )
	sparcv9_save_instr(sp, Rdest_num, Rsrc1 + Rsrc2);
	ENDDEF
	
IMPL( restore_imm )
	sparcv9_restore_instr(sp, Rdest_num, Rsrc1 + Simm16);
	ENDDEF

IMPL( restore_rrr )
	sparcv9_restore_instr(sp, Rdest_num, Rsrc1 + Rsrc2);
	ENDDEF





IMPL( saved )
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t *)(sp->specificp);

	if (V9_User == v9p->state) {
		v9p->post_precise_trap(sp, Sparcv9_trap_privileged_opcode);
		return;
	}
		
	v9p->cansave = INC_MOD(v9p->cansave, v9p->nwins);
        if (v9p->otherwin == 0)
		v9p->canrestore = DEC_MOD(v9p->canrestore, v9p->nwins);
	else
		v9p->otherwin = DEC_MOD(v9p->otherwin, v9p->nwins);
	NEXT_INSTN(sp);
	ENDDEF


IMPL( restored )
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t *)(sp->specificp);

	if (V9_User == v9p->state) {
		v9p->post_precise_trap(sp, Sparcv9_trap_privileged_opcode);
		return;
	}
		
	v9p->canrestore = INC_MOD(v9p->canrestore, v9p->nwins);
        if (v9p->otherwin == 0)
		v9p->cansave = DEC_MOD(v9p->cansave, v9p->nwins);
	else
		v9p->otherwin = DEC_MOD(v9p->otherwin, v9p->nwins);

	if (v9p->cleanwin < (v9p->nwins-1))
		v9p->cleanwin = v9p->cleanwin + 1;

	NEXT_INSTN(sp);
	ENDDEF


IMPL( flushw )
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t *)(sp->specificp);
	sparcv9_trap_type_t tt;

	if (v9p->cansave == (v9p->nwins-2)) {
		NEXT_INSTN(sp);
		return;
	}
	if (v9p->otherwin != 0) {
		tt = Sparcv9_trap_spill_0_other | (v9p->wstate_other<<2);
	} else {
		tt = Sparcv9_trap_spill_0_normal | (v9p->wstate_normal<<2);
	}
	v9p->post_precise_trap(sp, tt);
	ENDDEF



	/*
	 * Return
	 */

IMPL( return_imm )
        sparcv9_return_instr(sp, Rsrc1 + Simm16);
        ENDDEF

IMPL( return_rrr )
        sparcv9_return_instr(sp, Rsrc1 + Rsrc2);
        ENDDEF

/* ------------------------------------------------------------ */

	/*
	 * Done / Retry
	 */

IMPL( done_retry )
	sparcv9_cpu_t * v9p;
        v9p = (sparcv9_cpu_t *)(sp->specificp);
	v9p->done_retry(sp, (bool_t)Misc32);	/* true if done instruction */
	ENDDEF


/* ------------------------------------------------------------ */

	/*
	 * Instruction cache flushing
	 *
	 * May be implementation dependent whether this causes
	 * an ITLB lookup or not ....
	 * .... most sparc cpus just use this to flush instructions from
	 * the pipe. We use this to ensure the xicache is coherent (e.g. like a very
	 * deep pipe).
	 */


IMPL(iflush_rr)
	tvaddr_t va;
	va = (Rsrc1 + Rsrc2) & ~(tvaddr_t)7;
	ss_iflush_by_va(sp, va, -1 , SS_FLUSH_GRAN); /* -1 for implicit ASI */
	NEXT_INSTN(sp);
	ENDDEF

IMPL(iflush_imm)
	tvaddr_t va;
	va = (Rsrc1 + Simm16) & ~(tvaddr_t)7;
	ss_iflush_by_va(sp, va, -1 , SS_FLUSH_GRAN); /* -1 for implicit ASI */
	NEXT_INSTN(sp);
	ENDDEF

/* ------------------------------------------------------------ */

	/*
	 * ASI loads and stores
	 */


	/* immediate forms */

IMPL(asi_reg_imm)
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
	v9p->asi_access( sp, ASI_op, ASI_Rdest, sp->v9_asi, Rsrc1, Simm16, USE_ASI_REG );
	ENDDEF

IMPL(asi_reg)
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
	v9p->asi_access( sp, ASI_op, ASI_Rdest, sp->v9_asi, Rsrc1, Rsrc2, USE_ASI_REG );
	ENDDEF

IMPL(asi_num)
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
	v9p->asi_access( sp, ASI_op, ASI_Rdest, ASI_num, Rsrc1, Rsrc2, NO_FLAG );
	ENDDEF

IMPL(memop_rrr)
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
	v9p->asi_access( sp, ASI_op, ASI_Rdest, V9_ASI_IMPLICIT, Rsrc1, Rsrc2, NO_FLAG );
	ENDDEF

IMPL(memop_imm)
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
	v9p->asi_access( sp, ASI_op, ASI_Rdest, V9_ASI_IMPLICIT, Rsrc1, Simm16, NO_FLAG );
	ENDDEF

IMPL(fp64asi_imm)
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
#ifndef FP_DECODE_DISABLED
	if (!v9p->fpu_on) {
		v9p->post_precise_trap(sp, Sparcv9_trap_fp_disabled);
		return;
	}
#endif /* FP_DECODE_DISABLED */
	v9p->asi_access( sp, ASI_op, ASI_Rdest, sp->v9_asi, Rsrc1, Simm16, NO_FLAG );
	ENDDEF

IMPL(fp64asi_rrr)
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
#ifndef FP_DECODE_DISABLED
	if (!v9p->fpu_on) {
		v9p->post_precise_trap(sp, Sparcv9_trap_fp_disabled);
		return;
	}
#endif /* FP_DECODE_DISABLED */
	v9p->asi_access( sp, ASI_op, ASI_Rdest, ASI_num, Rsrc1, Rsrc2, NO_FLAG );
	ENDDEF

IMPL(ldfsr_imm)
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
#ifndef FP_DECODE_DISABLED
	if (!v9p->fpu_on) {
		v9p->post_precise_trap(sp, Sparcv9_trap_fp_disabled);
		return;
	}
#endif /* FP_DECODE_DISABLED */
	v9p->asi_access( sp, MA_V9_LdFSR|MA_Size32, NULL, V9_ASI_IMPLICIT, Rsrc1, Simm16, NO_FLAG );
	ENDDEF

IMPL(ldxfsr_imm)
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
#ifndef FP_DECODE_DISABLED
	if (!v9p->fpu_on) {
		v9p->post_precise_trap(sp, Sparcv9_trap_fp_disabled);
		return;
	}
#endif /* FP_DECODE_DISABLED */
	v9p->asi_access( sp, MA_V9_LdXFSR|MA_Size64, NULL, V9_ASI_IMPLICIT, Rsrc1, Simm16, NO_FLAG );
	ENDDEF


IMPL(stfsr_imm)
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
#ifndef FP_DECODE_DISABLED
	if (!v9p->fpu_on) {
		v9p->post_precise_trap(sp, Sparcv9_trap_fp_disabled);
		return;
	}
#endif /* FP_DECODE_DISABLED */
	v9p->asi_access( sp, MA_V9_StFSR|MA_Size32, NULL, V9_ASI_IMPLICIT, Rsrc1, Simm16, NO_FLAG );
	ENDDEF

IMPL(stxfsr_imm)
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
#ifndef FP_DECODE_DISABLED
	if (!v9p->fpu_on) {
		v9p->post_precise_trap(sp, Sparcv9_trap_fp_disabled);
		return;
	}
#endif /* FP_DECODE_DISABLED */
	v9p->asi_access( sp, MA_V9_StXFSR|MA_Size64, NULL, V9_ASI_IMPLICIT, Rsrc1, Simm16, NO_FLAG );
	ENDDEF


IMPL(ldfsr_rr)
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
#ifndef FP_DECODE_DISABLED
	if (!v9p->fpu_on) {
		v9p->post_precise_trap(sp, Sparcv9_trap_fp_disabled);
		return;
	}
#endif /* FP_DECODE_DISABLED */
	v9p->asi_access( sp, MA_V9_LdFSR|MA_Size32, NULL, V9_ASI_IMPLICIT, Rsrc1, Rsrc2, NO_FLAG );
	ENDDEF

IMPL(ldxfsr_rr)
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
#ifndef FP_DECODE_DISABLED
	if (!v9p->fpu_on) {
		v9p->post_precise_trap(sp, Sparcv9_trap_fp_disabled);
		return;
	}
#endif /* FP_DECODE_DISABLED */
	v9p->asi_access( sp, MA_V9_LdXFSR|MA_Size64, NULL, V9_ASI_IMPLICIT, Rsrc1, Rsrc2, NO_FLAG );
	ENDDEF


IMPL(stfsr_rr)
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
#ifndef FP_DECODE_DISABLED
	if (!v9p->fpu_on) {
		v9p->post_precise_trap(sp, Sparcv9_trap_fp_disabled);
		return;
	}
#endif /* FP_DECODE_DISABLED */
	v9p->asi_access( sp, MA_V9_StFSR|MA_Size32, NULL, V9_ASI_IMPLICIT, Rsrc1, Rsrc2, NO_FLAG );
	ENDDEF

IMPL(stxfsr_rr)
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
#ifndef FP_DECODE_DISABLED
	if (!v9p->fpu_on) {
		v9p->post_precise_trap(sp, Sparcv9_trap_fp_disabled);
		return;
	}
#endif /* FP_DECODE_DISABLED */
	v9p->asi_access( sp, MA_V9_StXFSR|MA_Size64, NULL, V9_ASI_IMPLICIT, Rsrc1, Rsrc2, NO_FLAG );
	ENDDEF


/* ------------------------------------------------------------ */

/*	Floating point branches.				*/





	/*
	 * Instruction: sparcv9_fbule_fcc0
	 */

#if !defined(HAS_NATIVE_sparcv9_fbule_fcc0)	/* { */

IMPL(fbule_fcc0)
#ifndef FP_DECODE_DISABLED
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
	if (!v9p->fpu_on) {
		v9p->post_precise_trap(sp, Sparcv9_trap_fp_disabled);
		return;
	}
#endif /* FP_DECODE_DISABLED */
	if (V9_FSR_FCC0(sp->v9_fsr_ctrl) != V9_fcc_g) {
		tvaddr_t tpc = Rpc + SBRoffset32;
		Rpc = Rnpc;
		Rnpc = tpc;
		return;
	}
	ENDI

#endif	/* } */





	/*
	 * Instruction: sparcv9_fbg_fcc0
	 */

#if !defined(HAS_NATIVE_sparcv9_fbg_fcc0)	/* { */

IMPL(fbg_fcc0)
#ifndef FP_DECODE_DISABLED
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
	if (!v9p->fpu_on) {
		v9p->post_precise_trap(sp, Sparcv9_trap_fp_disabled);
		return;
	}
#endif /* FP_DECODE_DISABLED */
	if (V9_FSR_FCC0(sp->v9_fsr_ctrl) == V9_fcc_g) {
		tvaddr_t tpc = Rpc + SBRoffset32;
		Rpc = Rnpc;
		Rnpc = tpc;
		return;
	}
	ENDI

#endif	/* } */





	/*
	 * Instruction: sparcv9_fblg_fcc0
	 */

#if !defined(HAS_NATIVE_sparcv9_fblg_fcc0)	/* { */

IMPL(fblg_fcc0)
	int cc = V9_FSR_FCC0(sp->v9_fsr_ctrl);
#ifndef FP_DECODE_DISABLED
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
	if (!v9p->fpu_on) {
		v9p->post_precise_trap(sp, Sparcv9_trap_fp_disabled);
		return;
	}
#endif /* FP_DECODE_DISABLED */
	if ( cc == V9_fcc_l || cc == V9_fcc_g ) {
		tvaddr_t tpc = Rpc + SBRoffset32;
		Rpc = Rnpc;
		Rnpc = tpc;
		return;
	}
	ENDI

#endif	/* } */





	/*
	 * Instruction: sparcv9_fble_fcc0
	 */

#if !defined(HAS_NATIVE_sparcv9_fble_fcc0)	/* { */

IMPL(fble_fcc0)
	int cc = V9_FSR_FCC0(sp->v9_fsr_ctrl);
#ifndef FP_DECODE_DISABLED
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
	if (!v9p->fpu_on) {
		v9p->post_precise_trap(sp, Sparcv9_trap_fp_disabled);
		return;
	}
#endif /* FP_DECODE_DISABLED */
	if ( cc == V9_fcc_e || cc == V9_fcc_l ) {
		tvaddr_t tpc = Rpc + SBRoffset32;
		Rpc = Rnpc;
		Rnpc = tpc;
		return;
	}
	ENDI

#endif	/* } */





	/*
	 * Instruction: sparcv9_fbge_fcc0
	 */

#if !defined(HAS_NATIVE_sparcv9_fbge_fcc0)	/* { */

IMPL(fbge_fcc0)
	int cc = V9_FSR_FCC0(sp->v9_fsr_ctrl);
#ifndef FP_DECODE_DISABLED
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
	if (!v9p->fpu_on) {
		v9p->post_precise_trap(sp, Sparcv9_trap_fp_disabled);
		return;
	}
#endif /* FP_DECODE_DISABLED */
	if ( cc == V9_fcc_g || cc == V9_fcc_e ) {
		tvaddr_t tpc = Rpc + SBRoffset32;
		Rpc = Rnpc;
		Rnpc = tpc;
		return;
	}
	ENDI

#endif	/* } */





	/*
	 * Instruction: sparcv9_fbne_fcc0
	 */

#if !defined(HAS_NATIVE_sparcv9_fbne_fcc0)	/* { */

IMPL(fbne_fcc0)
	int cc = V9_FSR_FCC0(sp->v9_fsr_ctrl);
#ifndef FP_DECODE_DISABLED
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
	if (!v9p->fpu_on) {
		v9p->post_precise_trap(sp, Sparcv9_trap_fp_disabled);
		return;
	}
#endif /* FP_DECODE_DISABLED */
	if ( cc != V9_fcc_e ) {
		tvaddr_t tpc = Rpc + SBRoffset32;
		Rpc = Rnpc;
		Rnpc = tpc;
		return;
	}
	ENDI

#endif	/* } */





	/*
	 * Instruction: sparcv9_fbug_fcc0
	 */

#if !defined(HAS_NATIVE_sparcv9_fbug_fcc0)	/* { */

IMPL(fbug_fcc0)
	int cc = V9_FSR_FCC0(sp->v9_fsr_ctrl);
#ifndef FP_DECODE_DISABLED
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
	if (!v9p->fpu_on) {
		v9p->post_precise_trap(sp, Sparcv9_trap_fp_disabled);
		return;
	}
#endif /* FP_DECODE_DISABLED */
	if ( cc == V9_fcc_u || cc == V9_fcc_g ) {
		tvaddr_t tpc = Rpc + SBRoffset32;
		Rpc = Rnpc;
		Rnpc = tpc;
		return;
	}
	ENDI

#endif	/* } */





	/*
	 * Instruction: sparcv9_fbul_fcc0
	 */

#if !defined(HAS_NATIVE_sparcv9_fbul_fcc0)	/* { */

IMPL(fbul_fcc0)
	int cc = V9_FSR_FCC0(sp->v9_fsr_ctrl);
#ifndef FP_DECODE_DISABLED
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
	if (!v9p->fpu_on) {
		v9p->post_precise_trap(sp, Sparcv9_trap_fp_disabled);
		return;
	}
#endif /* FP_DECODE_DISABLED */
	if ( cc == V9_fcc_u || cc == V9_fcc_l ) {
		tvaddr_t tpc = Rpc + SBRoffset32;
		Rpc = Rnpc;
		Rnpc = tpc;
		return;
	}
	ENDI

#endif	/* } */





	/*
	 * Instruction: sparcv9_fbue_fcc0
	 */

#if !defined(HAS_NATIVE_sparcv9_fbue_fcc0)	/* { */

IMPL(fbue_fcc0)
	int cc = V9_FSR_FCC0(sp->v9_fsr_ctrl);
#ifndef FP_DECODE_DISABLED
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
	if (!v9p->fpu_on) {
		v9p->post_precise_trap(sp, Sparcv9_trap_fp_disabled);
		return;
	}
#endif /* FP_DECODE_DISABLED */
	if ( cc == V9_fcc_u || cc == V9_fcc_e ) {
		tvaddr_t tpc = Rpc + SBRoffset32;
		Rpc = Rnpc;
		Rnpc = tpc;
		return;
	}
	ENDI

#endif	/* } */





	/*
	 * Instruction: sparcv9_fbe_fcc0
	 */

#if !defined(HAS_NATIVE_sparcv9_fbe_fcc0)	/* { */

IMPL(fbe_fcc0)
#ifndef FP_DECODE_DISABLED
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
	if (!v9p->fpu_on) {
		v9p->post_precise_trap(sp, Sparcv9_trap_fp_disabled);
		return;
	}
#endif /* FP_DECODE_DISABLED */
	if ( V9_FSR_FCC0(sp->v9_fsr_ctrl) == V9_fcc_e ) {
		tvaddr_t tpc = Rpc + SBRoffset32;
		Rpc = Rnpc;
		Rnpc = tpc;
		return;
	}
	ENDI

#endif	/* } */





	/*
	 * Instruction: sparcv9_fbo_fcc0
	 */

#if !defined(HAS_NATIVE_sparcv9_fbo_fcc0)	/* { */

IMPL(fbo_fcc0)
#ifndef FP_DECODE_DISABLED
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
	if (!v9p->fpu_on) {
		v9p->post_precise_trap(sp, Sparcv9_trap_fp_disabled);
		return;
	}
#endif /* FP_DECODE_DISABLED */
	if ( V9_FSR_FCC0(sp->v9_fsr_ctrl) != V9_fcc_u ) {
		tvaddr_t tpc = Rpc + SBRoffset32;
		Rpc = Rnpc;
		Rnpc = tpc;
		return;
	}
	ENDI

#endif	/* } */





	/*
	 * Instruction: sparcv9_fbu_fcc0
	 */

#if !defined(HAS_NATIVE_sparcv9_fbu_fcc0)	/* { */

IMPL(fbu_fcc0)
#ifndef FP_DECODE_DISABLED
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
	if (!v9p->fpu_on) {
		v9p->post_precise_trap(sp, Sparcv9_trap_fp_disabled);
		return;
	}
#endif /* FP_DECODE_DISABLED */
	if ( V9_FSR_FCC0(sp->v9_fsr_ctrl) == V9_fcc_u ) {
		tvaddr_t tpc = Rpc + SBRoffset32;
		Rpc = Rnpc;
		Rnpc = tpc;
		return;
	}
	ENDI

#endif	/* } */





	/*
	 * Instruction: sparcv9_fbuge_fcc0
	 */

#if !defined(HAS_NATIVE_sparcv9_fbuge_fcc0)	/* { */

IMPL(fbuge_fcc0)
#ifndef FP_DECODE_DISABLED
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
	if (!v9p->fpu_on) {
		v9p->post_precise_trap(sp, Sparcv9_trap_fp_disabled);
		return;
	}
#endif /* FP_DECODE_DISABLED */
	if ( V9_FSR_FCC0(sp->v9_fsr_ctrl) != V9_fcc_l ) {
		tvaddr_t tpc = Rpc + SBRoffset32;
		Rpc = Rnpc;
		Rnpc = tpc;
		return;
	}
	ENDI

#endif	/* } */





	/*
	 * Instruction: sparcv9_fbvs_fcc0
	 */

#if !defined(HAS_NATIVE_sparcv9_fbvs_fcc0)	/* { */

IMPL(fbl_fcc0)
#ifndef FP_DECODE_DISABLED
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
	if (!v9p->fpu_on) {
		v9p->post_precise_trap(sp, Sparcv9_trap_fp_disabled);
		return;
	}
#endif /* FP_DECODE_DISABLED */
	if ( V9_FSR_FCC0(sp->v9_fsr_ctrl) == V9_fcc_l ) {
		tvaddr_t tpc = Rpc + SBRoffset32;
		Rpc = Rnpc;
		Rnpc = tpc;
		return;
	}
	ENDI

#endif	/* } */



	/*
	 * Instruction: sparcv9_fbule_fccN
	 */

#if !defined(HAS_NATIVE_sparcv9_fbule_fccN)	/* { */

IMPL(fbule_fccN)
#ifndef FP_DECODE_DISABLED
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
	if (!v9p->fpu_on) {
		v9p->post_precise_trap(sp, Sparcv9_trap_fp_disabled);
		return;
	}
#endif /* FP_DECODE_DISABLED */
	if (V9_FSR_FCCN(sp->v9_fsr_ctrl, SBRfcc) != V9_fcc_g) {
		tvaddr_t tpc = Rpc + SBRoffset32;
		Rpc = Rnpc;
		Rnpc = tpc;
		return;
	}
	ENDI

#endif	/* } */





	/*
	 * Instruction: sparcv9_fbg_fccN
	 */

#if !defined(HAS_NATIVE_sparcv9_fbg_fccN)	/* { */

IMPL(fbg_fccN)
#ifndef FP_DECODE_DISABLED
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
	if (!v9p->fpu_on) {
		v9p->post_precise_trap(sp, Sparcv9_trap_fp_disabled);
		return;
	}
#endif /* FP_DECODE_DISABLED */
	if (V9_FSR_FCCN(sp->v9_fsr_ctrl, SBRfcc) == V9_fcc_g) {
		tvaddr_t tpc = Rpc + SBRoffset32;
		Rpc = Rnpc;
		Rnpc = tpc;
		return;
	}
	ENDI

#endif	/* } */





	/*
	 * Instruction: sparcv9_fblg_fccN
	 */

#if !defined(HAS_NATIVE_sparcv9_fblg_fccN)	/* { */

IMPL(fblg_fccN)
	int cc = V9_FSR_FCCN(sp->v9_fsr_ctrl, SBRfcc);
#ifndef FP_DECODE_DISABLED
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
	if (!v9p->fpu_on) {
		v9p->post_precise_trap(sp, Sparcv9_trap_fp_disabled);
		return;
	}
#endif /* FP_DECODE_DISABLED */
	if ( cc == V9_fcc_l || cc == V9_fcc_g ) {
		tvaddr_t tpc = Rpc + SBRoffset32;
		Rpc = Rnpc;
		Rnpc = tpc;
		return;
	}
	ENDI

#endif	/* } */





	/*
	 * Instruction: sparcv9_fble_fccN
	 */

#if !defined(HAS_NATIVE_sparcv9_fble_fccN)	/* { */

IMPL(fble_fccN)
	int cc = V9_FSR_FCCN(sp->v9_fsr_ctrl, SBRfcc);
#ifndef FP_DECODE_DISABLED
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
	if (!v9p->fpu_on) {
		v9p->post_precise_trap(sp, Sparcv9_trap_fp_disabled);
		return;
	}
#endif /* FP_DECODE_DISABLED */
	if ( cc == V9_fcc_e || cc == V9_fcc_l ) {
		tvaddr_t tpc = Rpc + SBRoffset32;
		Rpc = Rnpc;
		Rnpc = tpc;
		return;
	}
	ENDI

#endif	/* } */





	/*
	 * Instruction: sparcv9_fbge_fccN
	 */

#if !defined(HAS_NATIVE_sparcv9_fbge_fccN)	/* { */

IMPL(fbge_fccN)
	int cc = V9_FSR_FCCN(sp->v9_fsr_ctrl, SBRfcc);
#ifndef FP_DECODE_DISABLED
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
	if (!v9p->fpu_on) {
		v9p->post_precise_trap(sp, Sparcv9_trap_fp_disabled);
		return;
	}
#endif /* FP_DECODE_DISABLED */
	if ( cc == V9_fcc_g || cc == V9_fcc_e ) {
		tvaddr_t tpc = Rpc + SBRoffset32;
		Rpc = Rnpc;
		Rnpc = tpc;
		return;
	}
	ENDI

#endif	/* } */





	/*
	 * Instruction: sparcv9_fbne_fccN
	 */

#if !defined(HAS_NATIVE_sparcv9_fbne_fccN)	/* { */

IMPL(fbne_fccN)
	int cc = V9_FSR_FCCN(sp->v9_fsr_ctrl, SBRfcc);
#ifndef FP_DECODE_DISABLED
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
	if (!v9p->fpu_on) {
		v9p->post_precise_trap(sp, Sparcv9_trap_fp_disabled);
		return;
	}
#endif /* FP_DECODE_DISABLED */
	if ( cc != V9_fcc_e ) {
		tvaddr_t tpc = Rpc + SBRoffset32;
		Rpc = Rnpc;
		Rnpc = tpc;
		return;
	}
	ENDI

#endif	/* } */





	/*
	 * Instruction: sparcv9_fbug_fccN
	 */

#if !defined(HAS_NATIVE_sparcv9_fbug_fccN)	/* { */

IMPL(fbug_fccN)
	int cc = V9_FSR_FCCN(sp->v9_fsr_ctrl, SBRfcc);
#ifndef FP_DECODE_DISABLED
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
	if (!v9p->fpu_on) {
		v9p->post_precise_trap(sp, Sparcv9_trap_fp_disabled);
		return;
	}
#endif /* FP_DECODE_DISABLED */
	if ( cc == V9_fcc_u || cc == V9_fcc_g ) {
		tvaddr_t tpc = Rpc + SBRoffset32;
		Rpc = Rnpc;
		Rnpc = tpc;
		return;
	}
	ENDI

#endif	/* } */





	/*
	 * Instruction: sparcv9_fbul_fccN
	 */

#if !defined(HAS_NATIVE_sparcv9_fbul_fccN)	/* { */

IMPL(fbul_fccN)
	int cc = V9_FSR_FCCN(sp->v9_fsr_ctrl, SBRfcc);
#ifndef FP_DECODE_DISABLED
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
	if (!v9p->fpu_on) {
		v9p->post_precise_trap(sp, Sparcv9_trap_fp_disabled);
		return;
	}
#endif /* FP_DECODE_DISABLED */
	if ( cc == V9_fcc_u || cc == V9_fcc_l ) {
		tvaddr_t tpc = Rpc + SBRoffset32;
		Rpc = Rnpc;
		Rnpc = tpc;
		return;
	}
	ENDI

#endif	/* } */





	/*
	 * Instruction: sparcv9_fbue_fccN
	 */

#if !defined(HAS_NATIVE_sparcv9_fbue_fccN)	/* { */

IMPL(fbue_fccN)
	int cc = V9_FSR_FCCN(sp->v9_fsr_ctrl, SBRfcc);
#ifndef FP_DECODE_DISABLED
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
	if (!v9p->fpu_on) {
		v9p->post_precise_trap(sp, Sparcv9_trap_fp_disabled);
		return;
	}
#endif /* FP_DECODE_DISABLED */
	if ( cc == V9_fcc_u || cc == V9_fcc_e ) {
		tvaddr_t tpc = Rpc + SBRoffset32;
		Rpc = Rnpc;
		Rnpc = tpc;
		return;
	}
	ENDI

#endif	/* } */





	/*
	 * Instruction: sparcv9_fbe_fccN
	 */

#if !defined(HAS_NATIVE_sparcv9_fbe_fccN)	/* { */

IMPL(fbe_fccN)
#ifndef FP_DECODE_DISABLED
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
	if (!v9p->fpu_on) {
		v9p->post_precise_trap(sp, Sparcv9_trap_fp_disabled);
		return;
	}
#endif /* FP_DECODE_DISABLED */
	if ( V9_FSR_FCCN(sp->v9_fsr_ctrl, SBRfcc) == V9_fcc_e ) {
		tvaddr_t tpc = Rpc + SBRoffset32;
		Rpc = Rnpc;
		Rnpc = tpc;
		return;
	}
	ENDI

#endif	/* } */





	/*
	 * Instruction: sparcv9_fbo_fccN
	 */

#if !defined(HAS_NATIVE_sparcv9_fbo_fccN)	/* { */

IMPL(fbo_fccN)
#ifndef FP_DECODE_DISABLED
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
	if (!v9p->fpu_on) {
		v9p->post_precise_trap(sp, Sparcv9_trap_fp_disabled);
		return;
	}
#endif /* FP_DECODE_DISABLED */
	if ( V9_FSR_FCCN(sp->v9_fsr_ctrl, SBRfcc) != V9_fcc_u ) {
		tvaddr_t tpc = Rpc + SBRoffset32;
		Rpc = Rnpc;
		Rnpc = tpc;
		return;
	}
	ENDI

#endif	/* } */





	/*
	 * Instruction: sparcv9_fbu_fccN
	 */

#if !defined(HAS_NATIVE_sparcv9_fbu_fccN)	/* { */

IMPL(fbu_fccN)
#ifndef FP_DECODE_DISABLED
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
	if (!v9p->fpu_on) {
		v9p->post_precise_trap(sp, Sparcv9_trap_fp_disabled);
		return;
	}
#endif /* FP_DECODE_DISABLED */
	if ( V9_FSR_FCCN(sp->v9_fsr_ctrl, SBRfcc) == V9_fcc_u ) {
		tvaddr_t tpc = Rpc + SBRoffset32;
		Rpc = Rnpc;
		Rnpc = tpc;
		return;
	}
	ENDI

#endif	/* } */





	/*
	 * Instruction: sparcv9_fbuge_fccN
	 */

#if !defined(HAS_NATIVE_sparcv9_fbuge_fccN)	/* { */

IMPL(fbuge_fccN)
#ifndef FP_DECODE_DISABLED
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
	if (!v9p->fpu_on) {
		v9p->post_precise_trap(sp, Sparcv9_trap_fp_disabled);
		return;
	}
#endif /* FP_DECODE_DISABLED */
	if ( V9_FSR_FCCN(sp->v9_fsr_ctrl, SBRfcc) != V9_fcc_l ) {
		tvaddr_t tpc = Rpc + SBRoffset32;
		Rpc = Rnpc;
		Rnpc = tpc;
		return;
	}
	ENDI

#endif	/* } */





	/*
	 * Instruction: sparcv9_fbl_fccN
	 */

#if !defined(HAS_NATIVE_sparcv9_fbl_fccN)	/* { */

IMPL(fbl_fccN)
#ifndef FP_DECODE_DISABLED
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
	if (!v9p->fpu_on) {
		v9p->post_precise_trap(sp, Sparcv9_trap_fp_disabled);
		return;
	}
#endif /* FP_DECODE_DISABLED */
	if ( V9_FSR_FCCN(sp->v9_fsr_ctrl, SBRfcc) == V9_fcc_l ) {
		tvaddr_t tpc = Rpc + SBRoffset32;
		Rpc = Rnpc;
		Rnpc = tpc;
		return;
	}
	ENDI

#endif	/* } */








	/*
	 * Instruction: sparcv9_fbule_fcc0_an
	 */

#if !defined(HAS_NATIVE_sparcv9_fbule_fcc0_an)	/* { */

IMPL(fbule_fcc0_an)
#ifndef FP_DECODE_DISABLED
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
	if (!v9p->fpu_on) {
		v9p->post_precise_trap(sp, Sparcv9_trap_fp_disabled);
		return;
	}
#endif /* FP_DECODE_DISABLED */
	if (V9_FSR_FCC0(sp->v9_fsr_ctrl) != V9_fcc_g) {
		tvaddr_t tpc = Rpc + SBRoffset32;
		Rpc = Rnpc;
		Rnpc = tpc;
		return;
	}
	Rpc = Rnpc + 4;
	Rnpc = Rnpc + 8;
	ENDDEF

#endif	/* } */





	/*
	 * Instruction: sparcv9_fbg_fcc0_an
	 */

#if !defined(HAS_NATIVE_sparcv9_fbg_fcc0_an)	/* { */

IMPL(fbg_fcc0_an)
#ifndef FP_DECODE_DISABLED
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
	if (!v9p->fpu_on) {
		v9p->post_precise_trap(sp, Sparcv9_trap_fp_disabled);
		return;
	}
#endif /* FP_DECODE_DISABLED */
	if (V9_FSR_FCC0(sp->v9_fsr_ctrl) == V9_fcc_g) {
		tvaddr_t tpc = Rpc + SBRoffset32;
		Rpc = Rnpc;
		Rnpc = tpc;
		return;
	}
	Rpc = Rnpc + 4;
	Rnpc = Rnpc + 8;
	ENDDEF

#endif	/* } */





	/*
	 * Instruction: sparcv9_fblg_fcc0_an
	 */

#if !defined(HAS_NATIVE_sparcv9_fblg_fcc0_an)	/* { */

IMPL(fblg_fcc0_an)
	int cc = V9_FSR_FCC0(sp->v9_fsr_ctrl);
#ifndef FP_DECODE_DISABLED
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
	if (!v9p->fpu_on) {
		v9p->post_precise_trap(sp, Sparcv9_trap_fp_disabled);
		return;
	}
#endif /* FP_DECODE_DISABLED */
	if ( cc == V9_fcc_l || cc == V9_fcc_g ) {
		tvaddr_t tpc = Rpc + SBRoffset32;
		Rpc = Rnpc;
		Rnpc = tpc;
		return;
	}
	Rpc = Rnpc + 4;
	Rnpc = Rnpc + 8;
	ENDDEF

#endif	/* } */





	/*
	 * Instruction: sparcv9_fble_fcc0_an
	 */

#if !defined(HAS_NATIVE_sparcv9_fble_fcc0_an)	/* { */

IMPL(fble_fcc0_an)
	int cc = V9_FSR_FCC0(sp->v9_fsr_ctrl);
#ifndef FP_DECODE_DISABLED
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
	if (!v9p->fpu_on) {
		v9p->post_precise_trap(sp, Sparcv9_trap_fp_disabled);
		return;
	}
#endif /* FP_DECODE_DISABLED */
	if ( cc == V9_fcc_e || cc == V9_fcc_l ) {
		tvaddr_t tpc = Rpc + SBRoffset32;
		Rpc = Rnpc;
		Rnpc = tpc;
		return;
	}
	Rpc = Rnpc + 4;
	Rnpc = Rnpc + 8;
	ENDDEF

#endif	/* } */





	/*
	 * Instruction: sparcv9_fbge_fcc0_an
	 */

#if !defined(HAS_NATIVE_sparcv9_fbge_fcc0_an)	/* { */

IMPL(fbge_fcc0_an)
	int cc = V9_FSR_FCC0(sp->v9_fsr_ctrl);
#ifndef FP_DECODE_DISABLED
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
	if (!v9p->fpu_on) {
		v9p->post_precise_trap(sp, Sparcv9_trap_fp_disabled);
		return;
	}
#endif /* FP_DECODE_DISABLED */
	if ( cc == V9_fcc_g || cc == V9_fcc_e ) {
		tvaddr_t tpc = Rpc + SBRoffset32;
		Rpc = Rnpc;
		Rnpc = tpc;
		return;
	}
	Rpc = Rnpc + 4;
	Rnpc = Rnpc + 8;
	ENDDEF

#endif	/* } */





	/*
	 * Instruction: sparcv9_fbne_fcc0_an
	 */

#if !defined(HAS_NATIVE_sparcv9_fbne_fcc0_an)	/* { */

IMPL(fbne_fcc0_an)
	int cc = V9_FSR_FCC0(sp->v9_fsr_ctrl);
#ifndef FP_DECODE_DISABLED
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
	if (!v9p->fpu_on) {
		v9p->post_precise_trap(sp, Sparcv9_trap_fp_disabled);
		return;
	}
#endif /* FP_DECODE_DISABLED */
	if ( cc != V9_fcc_e ) {
		tvaddr_t tpc = Rpc + SBRoffset32;
		Rpc = Rnpc;
		Rnpc = tpc;
		return;
	}
	Rpc = Rnpc + 4;
	Rnpc = Rnpc + 8;
	ENDDEF

#endif	/* } */





	/*
	 * Instruction: sparcv9_fbug_fcc0_an
	 */

#if !defined(HAS_NATIVE_sparcv9_fbug_fcc0_an)	/* { */

IMPL(fbug_fcc0_an)
	int cc = V9_FSR_FCC0(sp->v9_fsr_ctrl);
#ifndef FP_DECODE_DISABLED
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
	if (!v9p->fpu_on) {
		v9p->post_precise_trap(sp, Sparcv9_trap_fp_disabled);
		return;
	}
#endif /* FP_DECODE_DISABLED */
	if ( cc == V9_fcc_u || cc == V9_fcc_g ) {
		tvaddr_t tpc = Rpc + SBRoffset32;
		Rpc = Rnpc;
		Rnpc = tpc;
		return;
	}
	Rpc = Rnpc + 4;
	Rnpc = Rnpc + 8;
	ENDDEF

#endif	/* } */





	/*
	 * Instruction: sparcv9_fbul_fcc0_an
	 */

#if !defined(HAS_NATIVE_sparcv9_fbul_fcc0_an)	/* { */

IMPL(fbul_fcc0_an)
	int cc = V9_FSR_FCC0(sp->v9_fsr_ctrl);
#ifndef FP_DECODE_DISABLED
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
	if (!v9p->fpu_on) {
		v9p->post_precise_trap(sp, Sparcv9_trap_fp_disabled);
		return;
	}
#endif /* FP_DECODE_DISABLED */
	if ( cc == V9_fcc_u || cc == V9_fcc_l ) {
		tvaddr_t tpc = Rpc + SBRoffset32;
		Rpc = Rnpc;
		Rnpc = tpc;
		return;
	}
	Rpc = Rnpc + 4;
	Rnpc = Rnpc + 8;
	ENDDEF

#endif	/* } */





	/*
	 * Instruction: sparcv9_fbue_fcc0_an
	 */

#if !defined(HAS_NATIVE_sparcv9_fbue_fcc0_an)	/* { */

IMPL(fbue_fcc0_an)
	int cc = V9_FSR_FCC0(sp->v9_fsr_ctrl);
#ifndef FP_DECODE_DISABLED
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
	if (!v9p->fpu_on) {
		v9p->post_precise_trap(sp, Sparcv9_trap_fp_disabled);
		return;
	}
#endif /* FP_DECODE_DISABLED */
	if ( cc == V9_fcc_u || cc == V9_fcc_e ) {
		tvaddr_t tpc = Rpc + SBRoffset32;
		Rpc = Rnpc;
		Rnpc = tpc;
		return;
	}
	Rpc = Rnpc + 4;
	Rnpc = Rnpc + 8;
	ENDDEF

#endif	/* } */





	/*
	 * Instruction: sparcv9_fbe_fcc0_an
	 */

#if !defined(HAS_NATIVE_sparcv9_fbe_fcc0_an)	/* { */

IMPL(fbe_fcc0_an)
#ifndef FP_DECODE_DISABLED
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
	if (!v9p->fpu_on) {
		v9p->post_precise_trap(sp, Sparcv9_trap_fp_disabled);
		return;
	}
#endif /* FP_DECODE_DISABLED */
	if ( V9_FSR_FCC0(sp->v9_fsr_ctrl) == V9_fcc_e ) {
		tvaddr_t tpc = Rpc + SBRoffset32;
		Rpc = Rnpc;
		Rnpc = tpc;
		return;
	}
	Rpc = Rnpc + 4;
	Rnpc = Rnpc + 8;
	ENDDEF

#endif	/* } */





	/*
	 * Instruction: sparcv9_fbo_fcc0_an
	 */

#if !defined(HAS_NATIVE_sparcv9_fbo_fcc0_an)	/* { */

IMPL(fbo_fcc0_an)
#ifndef FP_DECODE_DISABLED
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
	if (!v9p->fpu_on) {
		v9p->post_precise_trap(sp, Sparcv9_trap_fp_disabled);
		return;
	}
#endif /* FP_DECODE_DISABLED */
	if ( V9_FSR_FCC0(sp->v9_fsr_ctrl) != V9_fcc_u ) {
		tvaddr_t tpc = Rpc + SBRoffset32;
		Rpc = Rnpc;
		Rnpc = tpc;
		return;
	}
	Rpc = Rnpc + 4;
	Rnpc = Rnpc + 8;
	ENDDEF

#endif	/* } */





	/*
	 * Instruction: sparcv9_fbu_fcc0_an
	 */

#if !defined(HAS_NATIVE_sparcv9_fbu_fcc0_an)	/* { */

IMPL(fbu_fcc0_an)
#ifndef FP_DECODE_DISABLED
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
	if (!v9p->fpu_on) {
		v9p->post_precise_trap(sp, Sparcv9_trap_fp_disabled);
		return;
	}
#endif /* FP_DECODE_DISABLED */
	if ( V9_FSR_FCC0(sp->v9_fsr_ctrl) == V9_fcc_u ) {
		tvaddr_t tpc = Rpc + SBRoffset32;
		Rpc = Rnpc;
		Rnpc = tpc;
		return;
	}
	Rpc = Rnpc + 4;
	Rnpc = Rnpc + 8;
	ENDDEF

#endif	/* } */





	/*
	 * Instruction: sparcv9_fbuge_fcc0_an
	 */

#if !defined(HAS_NATIVE_sparcv9_fbuge_fcc0_an)	/* { */

IMPL(fbuge_fcc0_an)
#ifndef FP_DECODE_DISABLED
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
	if (!v9p->fpu_on) {
		v9p->post_precise_trap(sp, Sparcv9_trap_fp_disabled);
		return;
	}
#endif /* FP_DECODE_DISABLED */
	if ( V9_FSR_FCC0(sp->v9_fsr_ctrl) != V9_fcc_l ) {
		tvaddr_t tpc = Rpc + SBRoffset32;
		Rpc = Rnpc;
		Rnpc = tpc;
		return;
	}
	Rpc = Rnpc + 4;
	Rnpc = Rnpc + 8;
	ENDDEF

#endif	/* } */





	/*
	 * Instruction: sparcv9_fbvs_fcc0_an
	 */

#if !defined(HAS_NATIVE_sparcv9_fbvs_fcc0_an)	/* { */

IMPL(fbl_fcc0_an)
#ifndef FP_DECODE_DISABLED
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
	if (!v9p->fpu_on) {
		v9p->post_precise_trap(sp, Sparcv9_trap_fp_disabled);
		return;
	}
#endif /* FP_DECODE_DISABLED */
	if ( V9_FSR_FCC0(sp->v9_fsr_ctrl) == V9_fcc_l ) {
		tvaddr_t tpc = Rpc + SBRoffset32;
		Rpc = Rnpc;
		Rnpc = tpc;
		return;
	}
	Rpc = Rnpc + 4;
	Rnpc = Rnpc + 8;
	ENDDEF

#endif	/* } */






	/*
	 * Instruction: sparcv9_fbule_fccN_an
	 */

#if !defined(HAS_NATIVE_sparcv9_fbule_fccN_an)	/* { */

IMPL(fbule_fccN_an)
#ifndef FP_DECODE_DISABLED
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
	if (!v9p->fpu_on) {
		v9p->post_precise_trap(sp, Sparcv9_trap_fp_disabled);
		return;
	}
#endif /* FP_DECODE_DISABLED */
	if (V9_FSR_FCCN(sp->v9_fsr_ctrl, SBRfcc) != V9_fcc_g) {
		tvaddr_t tpc = Rpc + SBRoffset32;
		Rpc = Rnpc;
		Rnpc = tpc;
		return;
	}
	Rpc = Rnpc + 4;
	Rnpc = Rnpc + 8;
	ENDDEF

#endif	/* } */





	/*
	 * Instruction: sparcv9_fbg_fccN_an
	 */

#if !defined(HAS_NATIVE_sparcv9_fbg_fccN_an)	/* { */

IMPL(fbg_fccN_an)
#ifndef FP_DECODE_DISABLED
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
	if (!v9p->fpu_on) {
		v9p->post_precise_trap(sp, Sparcv9_trap_fp_disabled);
		return;
	}
#endif /* FP_DECODE_DISABLED */
	if (V9_FSR_FCCN(sp->v9_fsr_ctrl, SBRfcc) == V9_fcc_g) {
		tvaddr_t tpc = Rpc + SBRoffset32;
		Rpc = Rnpc;
		Rnpc = tpc;
		return;
	}
	Rpc = Rnpc + 4;
	Rnpc = Rnpc + 8;
	ENDDEF

#endif	/* } */





	/*
	 * Instruction: sparcv9_fblg_fccN_an
	 */

#if !defined(HAS_NATIVE_sparcv9_fblg_fccN_an)	/* { */

IMPL(fblg_fccN_an)
	int cc = V9_FSR_FCCN(sp->v9_fsr_ctrl, SBRfcc);
#ifndef FP_DECODE_DISABLED
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
	if (!v9p->fpu_on) {
		v9p->post_precise_trap(sp, Sparcv9_trap_fp_disabled);
		return;
	}
#endif /* FP_DECODE_DISABLED */
	if ( cc == V9_fcc_l || cc == V9_fcc_g ) {
		tvaddr_t tpc = Rpc + SBRoffset32;
		Rpc = Rnpc;
		Rnpc = tpc;
		return;
	}
	Rpc = Rnpc + 4;
	Rnpc = Rnpc + 8;
	ENDDEF

#endif	/* } */





	/*
	 * Instruction: sparcv9_fble_fccN_an
	 */

#if !defined(HAS_NATIVE_sparcv9_fble_fccN_an)	/* { */

IMPL(fble_fccN_an)
	int cc = V9_FSR_FCCN(sp->v9_fsr_ctrl, SBRfcc);
#ifndef FP_DECODE_DISABLED
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
	if (!v9p->fpu_on) {
		v9p->post_precise_trap(sp, Sparcv9_trap_fp_disabled);
		return;
	}
#endif /* FP_DECODE_DISABLED */
	if ( cc == V9_fcc_e || cc == V9_fcc_l ) {
		tvaddr_t tpc = Rpc + SBRoffset32;
		Rpc = Rnpc;
		Rnpc = tpc;
		return;
	}
	Rpc = Rnpc + 4;
	Rnpc = Rnpc + 8;
	ENDDEF

#endif	/* } */





	/*
	 * Instruction: sparcv9_fbge_fccN_an
	 */

#if !defined(HAS_NATIVE_sparcv9_fbge_fccN_an)	/* { */

IMPL(fbge_fccN_an)
	int cc = V9_FSR_FCCN(sp->v9_fsr_ctrl, SBRfcc);
#ifndef FP_DECODE_DISABLED
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
	if (!v9p->fpu_on) {
		v9p->post_precise_trap(sp, Sparcv9_trap_fp_disabled);
		return;
	}
#endif /* FP_DECODE_DISABLED */
	if ( cc == V9_fcc_g || cc == V9_fcc_e ) {
		tvaddr_t tpc = Rpc + SBRoffset32;
		Rpc = Rnpc;
		Rnpc = tpc;
		return;
	}
	Rpc = Rnpc + 4;
	Rnpc = Rnpc + 8;
	ENDDEF

#endif	/* } */





	/*
	 * Instruction: sparcv9_fbne_fccN_an
	 */

#if !defined(HAS_NATIVE_sparcv9_fbne_fccN_an)	/* { */

IMPL(fbne_fccN_an)
	int cc = V9_FSR_FCCN(sp->v9_fsr_ctrl, SBRfcc);
#ifndef FP_DECODE_DISABLED
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
	if (!v9p->fpu_on) {
		v9p->post_precise_trap(sp, Sparcv9_trap_fp_disabled);
		return;
	}
#endif /* FP_DECODE_DISABLED */
	if ( cc != V9_fcc_e ) {
		tvaddr_t tpc = Rpc + SBRoffset32;
		Rpc = Rnpc;
		Rnpc = tpc;
		return;
	}
	Rpc = Rnpc + 4;
	Rnpc = Rnpc + 8;
	ENDDEF

#endif	/* } */





	/*
	 * Instruction: sparcv9_fbug_fccN_an
	 */

#if !defined(HAS_NATIVE_sparcv9_fbug_fccN_an)	/* { */

IMPL(fbug_fccN_an)
	int cc = V9_FSR_FCCN(sp->v9_fsr_ctrl, SBRfcc);
#ifndef FP_DECODE_DISABLED
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
	if (!v9p->fpu_on) {
		v9p->post_precise_trap(sp, Sparcv9_trap_fp_disabled);
		return;
	}
#endif /* FP_DECODE_DISABLED */
	if ( cc == V9_fcc_u || cc == V9_fcc_g ) {
		tvaddr_t tpc = Rpc + SBRoffset32;
		Rpc = Rnpc;
		Rnpc = tpc;
		return;
	}
	Rpc = Rnpc + 4;
	Rnpc = Rnpc + 8;
	ENDDEF

#endif	/* } */





	/*
	 * Instruction: sparcv9_fbul_fccN_an
	 */

#if !defined(HAS_NATIVE_sparcv9_fbul_fccN_an)	/* { */

IMPL(fbul_fccN_an)
	int cc = V9_FSR_FCCN(sp->v9_fsr_ctrl, SBRfcc);
#ifndef FP_DECODE_DISABLED
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
	if (!v9p->fpu_on) {
		v9p->post_precise_trap(sp, Sparcv9_trap_fp_disabled);
		return;
	}
#endif /* FP_DECODE_DISABLED */
	if ( cc == V9_fcc_u || cc == V9_fcc_l ) {
		tvaddr_t tpc = Rpc + SBRoffset32;
		Rpc = Rnpc;
		Rnpc = tpc;
		return;
	}
	Rpc = Rnpc + 4;
	Rnpc = Rnpc + 8;
	ENDDEF

#endif	/* } */





	/*
	 * Instruction: sparcv9_fbue_fccN_an
	 */

#if !defined(HAS_NATIVE_sparcv9_fbue_fccN_an)	/* { */

IMPL(fbue_fccN_an)
	int cc = V9_FSR_FCCN(sp->v9_fsr_ctrl, SBRfcc);
#ifndef FP_DECODE_DISABLED
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
	if (!v9p->fpu_on) {
		v9p->post_precise_trap(sp, Sparcv9_trap_fp_disabled);
		return;
	}
#endif /* FP_DECODE_DISABLED */
	if ( cc == V9_fcc_u || cc == V9_fcc_e ) {
		tvaddr_t tpc = Rpc + SBRoffset32;
		Rpc = Rnpc;
		Rnpc = tpc;
		return;
	}
	Rpc = Rnpc + 4;
	Rnpc = Rnpc + 8;
	ENDDEF

#endif	/* } */





	/*
	 * Instruction: sparcv9_fbe_fccN_an
	 */

#if !defined(HAS_NATIVE_sparcv9_fbe_fccN_an)	/* { */

IMPL(fbe_fccN_an)
#ifndef FP_DECODE_DISABLED
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
	if (!v9p->fpu_on) {
		v9p->post_precise_trap(sp, Sparcv9_trap_fp_disabled);
		return;
	}
#endif /* FP_DECODE_DISABLED */
	if ( V9_FSR_FCCN(sp->v9_fsr_ctrl, SBRfcc) == V9_fcc_e ) {
		tvaddr_t tpc = Rpc + SBRoffset32;
		Rpc = Rnpc;
		Rnpc = tpc;
		return;
	}
	Rpc = Rnpc + 4;
	Rnpc = Rnpc + 8;
	ENDDEF

#endif	/* } */





	/*
	 * Instruction: sparcv9_fbo_fccN_an
	 */

#if !defined(HAS_NATIVE_sparcv9_fbo_fccN_an)	/* { */

IMPL(fbo_fccN_an)
#ifndef FP_DECODE_DISABLED
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
	if (!v9p->fpu_on) {
		v9p->post_precise_trap(sp, Sparcv9_trap_fp_disabled);
		return;
	}
#endif /* FP_DECODE_DISABLED */
	if ( V9_FSR_FCCN(sp->v9_fsr_ctrl, SBRfcc) != V9_fcc_u ) {
		tvaddr_t tpc = Rpc + SBRoffset32;
		Rpc = Rnpc;
		Rnpc = tpc;
		return;
	}
	Rpc = Rnpc + 4;
	Rnpc = Rnpc + 8;
	ENDDEF

#endif	/* } */





	/*
	 * Instruction: sparcv9_fbu_fccN_an
	 */

#if !defined(HAS_NATIVE_sparcv9_fbu_fccN_an)	/* { */

IMPL(fbu_fccN_an)
#ifndef FP_DECODE_DISABLED
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
	if (!v9p->fpu_on) {
		v9p->post_precise_trap(sp, Sparcv9_trap_fp_disabled);
		return;
	}
#endif /* FP_DECODE_DISABLED */
	if ( V9_FSR_FCCN(sp->v9_fsr_ctrl, SBRfcc) == V9_fcc_u ) {
		tvaddr_t tpc = Rpc + SBRoffset32;
		Rpc = Rnpc;
		Rnpc = tpc;
		return;
	}
	Rpc = Rnpc + 4;
	Rnpc = Rnpc + 8;
	ENDDEF

#endif	/* } */





	/*
	 * Instruction: sparcv9_fbuge_fccN_an
	 */

#if !defined(HAS_NATIVE_sparcv9_fbuge_fccN_an)	/* { */

IMPL(fbuge_fccN_an)
#ifndef FP_DECODE_DISABLED
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
	if (!v9p->fpu_on) {
		v9p->post_precise_trap(sp, Sparcv9_trap_fp_disabled);
		return;
	}
#endif /* FP_DECODE_DISABLED */
	if ( V9_FSR_FCCN(sp->v9_fsr_ctrl, SBRfcc) != V9_fcc_l ) {
		tvaddr_t tpc = Rpc + SBRoffset32;
		Rpc = Rnpc;
		Rnpc = tpc;
		return;
	}
	Rpc = Rnpc + 4;
	Rnpc = Rnpc + 8;
	ENDDEF

#endif	/* } */





	/*
	 * Instruction: sparcv9_fbl_fccN_an
	 */

#if !defined(HAS_NATIVE_sparcv9_fbl_fccN_an)	/* { */

IMPL(fbl_fccN_an)
#ifndef FP_DECODE_DISABLED
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
	if (!v9p->fpu_on) {
		v9p->post_precise_trap(sp, Sparcv9_trap_fp_disabled);
		return;
	}
#endif /* FP_DECODE_DISABLED */
	if ( V9_FSR_FCCN(sp->v9_fsr_ctrl, SBRfcc) == V9_fcc_l ) {
		tvaddr_t tpc = Rpc + SBRoffset32;
		Rpc = Rnpc;
		Rnpc = tpc;
		return;
	}
	Rpc = Rnpc + 4;
	Rnpc = Rnpc + 8;
	ENDDEF

#endif	/* } */


IMPL(illtrap)
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);

	v9p->post_precise_trap(sp, Sparcv9_trap_illegal_instruction);
	ENDDEF

/* ------------------------------------------------------------ */

/*	Miscellaneous stuff ... not real instructions, but executed that way */


IMPL(illegal_instruction)
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
#define	IBUF	160
	char ibuf[IBUF];
/*
 * This to limit spewing of warnings about invalid instructions.  Each
 * opcode (as determined by bits 24-19) has a limit of 40 (actually
 * INV_INST_LIMIT) error reports.  Feel free to replace this code with
 * something better.
 */
#define INV_INST_LIMIT 40
#define INV_INST_SIZE 64
#define OP_EXTR(inst) (((inst) >> 19) & 0x3f)
	 /*  statics init to zero */
	static int invalid_instruction_count[INV_INST_SIZE];

DBGILLINST(
	sparcv9_idis(ibuf, IBUF, xcip->rawi, sp->pc);
	if (invalid_instruction_count[OP_EXTR(xcip->rawi)]++ < INV_INST_LIMIT) {
		lprintf(sp->gid, "illegal instruction pc=0x%llx "
		    "instn=%08x: %s\n", sp->pc, xcip->rawi, ibuf);
	}
);
	v9p->post_precise_trap(sp, Sparcv9_trap_illegal_instruction);
#undef	IBUF
	ENDDEF


IMPL(fp_exception_instruction)
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);
#define	IBUF	160
	char ibuf[IBUF];

	if (!v9p->fpu_on) {
		v9p->post_precise_trap(sp, Sparcv9_trap_fp_disabled);
		return;
	}

DBGILLINST(
	sparcv9_idis(ibuf, IBUF, xcip->rawi, sp->pc);
	lprintf(sp->gid, "unimplemented fp op pc=0x%llx instn=%08x: %s\n", sp->pc, xcip->rawi, ibuf);
);

	ASSERT( xcip->di.ill_reason == SPARCv9_FTT_unimplemented_FPop ||
	    xcip->di.ill_reason == SPARCv9_FTT_invalid_fp_register);
	sp->v9_fsr_ctrl &= ~V9_FSR_FTT_MASK;
#ifdef PROCESSOR_SUPPORTS_QUADFP /* { */
	sp->v9_fsr_ctrl |= xcip->di.ill_reason << V9_FSR_FTT_SHIFT;
#else /* } { */
	/* If no quad FP, only report unimp. */
	sp->v9_fsr_ctrl |= SPARCv9_FTT_unimplemented_FPop << V9_FSR_FTT_SHIFT;
#endif /* } */

	v9p->post_precise_trap(sp, Sparcv9_trap_fp_exception_other);
#undef	IBUF

	ENDDEF


#if 0
IMPL(fcmps_fcc0)
IMPL(fcmps_fcc1)
IMPL(fcmps_fcc2)
IMPL(fcmps_fcc3)
IMPL(fcmpd_fcc0)
IMPL(fcmpd_fcc1)
IMPL(fcmpd_fcc2)
IMPL(fcmpd_fcc3)
IMPL(fcmpes_fcc0)
IMPL(fcmpes_fcc1)
IMPL(fcmpes_fcc2)
IMPL(fcmpes_fcc3)
IMPL(fcmped_fcc0)
IMPL(fcmped_fcc1)
IMPL(fcmped_fcc2)
IMPL(fcmped_fcc3)
#endif

/*
 * Tagged add and subtract.
 */

#if !defined(HAS_NATIVE_sparcv9_tadd_co_imm)	/* { */

IMPL(tadd_co_imm)
	int64_t s1 = Rsrc1;
	int64_t s2 = Simm16;
	int64_t d;
	uint64_t v, c;
	uint32_t icc_v;

	d = s1 + s2;

	v = (s1 & s2 & ~d) | (~s1 & ~s2 & d);
	c = (s1 & s2) | (~d & (s1 | s2));

	icc_v = ((v >> 31) & 1) | (((s1 | s2) >> 1) & 1) | ((s1 | s2) & 1);

	sp->v9_ccr  = V9_xcc_v((v >> 63) & 1);
	sp->v9_ccr |= V9_icc_v(icc_v);
	sp->v9_ccr |= V9_xcc_c((c >> 63) & 1);
	sp->v9_ccr |= V9_icc_c((c >> 31) & 1);
	sp->v9_ccr |= V9_xcc_n((d >> 63) & 1);
	sp->v9_ccr |= V9_icc_n((d >> 31) & 1);
	sp->v9_ccr |= V9_xcc_z(d ? 0 : 1);
	sp->v9_ccr |= V9_icc_z((d & MASK64(31,0)) ? 0 : 1);
	if (!Zero_Reg(Rdest_num))
		Rdest = d;
	ENDI

#endif	/* } */

#if !defined(HAS_NATIVE_sparcv9_tadd_co_rrr)	/* { */

IMPL(tadd_co_rrr)
	uint64_t s1 = Rsrc1, s2 = Rsrc2, d;
	uint64_t v, c;
	uint32_t icc_v;

	d = Rsrc1 + Rsrc2;

	v = (s1 & s2 & ~d) | (~s1 & ~s2 & d);
	c = (s1 & s2) | (~d & (s1 | s2));

	icc_v = ((v >> 31) & 1) | (((s1 | s2) >> 1) & 1) | ((s1 | s2) & 1);

	sp->v9_ccr  = V9_xcc_v((v >> 63) & 1);
	sp->v9_ccr |= V9_icc_v(icc_v);
	sp->v9_ccr |= V9_xcc_c((c >> 63) & 1);
	sp->v9_ccr |= V9_icc_c((c >> 31) & 1);
	sp->v9_ccr |= V9_xcc_n((d >> 63) & 1);
	sp->v9_ccr |= V9_icc_n((d >> 31) & 1);
	sp->v9_ccr |= V9_xcc_z(d ? 0 : 1);
	sp->v9_ccr |= V9_icc_z((d & MASK64(31,0)) ? 0 : 1);
	if (!Zero_Reg(Rdest_num))
		Rdest = d;
	ENDI

#endif	/* } */


#if !defined(HAS_NATIVE_sparcv9_tadd_co_tv_imm)	/* { */

IMPL(tadd_co_tv_imm)
	int64_t s1 = Rsrc1;
	int64_t s2 = Simm16;
	int64_t d;
	uint64_t v, c;
	uint32_t icc_v;

	d = s1 + s2;

	v = (s1 & s2 & ~d) | (~s1 & ~s2 & d);
	c = (s1 & s2) | (~d & (s1 | s2));

	icc_v = ((v >> 31) & 1) | (((s1 | s2) >> 1) & 1) | ((s1 | s2) & 1);

	if (icc_v) {
		sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);

		v9p->post_precise_trap(sp, Sparcv9_trap_tag_overflow);
		return;
	}

	sp->v9_ccr  = V9_xcc_v((v >> 63) & 1);
	sp->v9_ccr |= V9_icc_v(icc_v);
	sp->v9_ccr |= V9_xcc_c((c >> 63) & 1);
	sp->v9_ccr |= V9_icc_c((c >> 31) & 1);
	sp->v9_ccr |= V9_xcc_n((d >> 63) & 1);
	sp->v9_ccr |= V9_icc_n((d >> 31) & 1);
	sp->v9_ccr |= V9_xcc_z(d ? 0 : 1);
	sp->v9_ccr |= V9_icc_z((d & MASK64(31,0)) ? 0 : 1);
	if (!Zero_Reg(Rdest_num))
		Rdest = d;
	ENDI

#endif	/* } */

#if !defined(HAS_NATIVE_sparcv9_tadd_co_tv_rrr)	/* { */

IMPL(tadd_co_tv_rrr)
	uint64_t s1 = Rsrc1, s2 = Rsrc2, d;
	uint64_t v, c;
	uint32_t icc_v;

	d = Rsrc1 + Rsrc2;

	v = (s1 & s2 & ~d) | (~s1 & ~s2 & d);
	c = (s1 & s2) | (~d & (s1 | s2));

	icc_v = ((v >> 31) & 1) | (((s1 | s2) >> 1) & 1) | ((s1 | s2) & 1);

	if (icc_v) {
		sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);

		v9p->post_precise_trap(sp, Sparcv9_trap_tag_overflow);
		return;
	}

	sp->v9_ccr  = V9_xcc_v((v >> 63) & 1);
	sp->v9_ccr |= V9_icc_v(icc_v);
	sp->v9_ccr |= V9_xcc_c((c >> 63) & 1);
	sp->v9_ccr |= V9_icc_c((c >> 31) & 1);
	sp->v9_ccr |= V9_xcc_n((d >> 63) & 1);
	sp->v9_ccr |= V9_icc_n((d >> 31) & 1);
	sp->v9_ccr |= V9_xcc_z(d ? 0 : 1);
	sp->v9_ccr |= V9_icc_z((d & MASK64(31,0)) ? 0 : 1);
	if (!Zero_Reg(Rdest_num))
		Rdest = d;
	ENDI

#endif	/* } */


#if !defined(HAS_NATIVE_sparcv9_tsub_co_imm)	/* { */

IMPL(tsub_co_imm)
	int64_t s1 = Rsrc1;
	int64_t s2 = Simm16;
	int64_t d;
	uint64_t v, c;
	uint32_t icc_v;

	d = s1 - s2;

	v = (s1 & ~s2 & ~d) | (~s1 & s2 & d);
	c = (~s1 & s2) | (d & (~s1 | s2));

	icc_v = ((v >> 31) & 1) | (((s1 | s2) >> 1) & 1) | ((s1 | s2) & 1);

	sp->v9_ccr  = V9_xcc_v((v >> 63) & 1);
	sp->v9_ccr |= V9_icc_v(icc_v);
	sp->v9_ccr |= V9_xcc_c((c >> 63) & 1);
	sp->v9_ccr |= V9_icc_c((c >> 31) & 1);
	sp->v9_ccr |= V9_xcc_n((d >> 63) & 1);
	sp->v9_ccr |= V9_icc_n((d >> 31) & 1);
	sp->v9_ccr |= V9_xcc_z(d ? 0 : 1);
	sp->v9_ccr |= V9_icc_z((d & MASK64(31,0)) ? 0 : 1);
	if (!Zero_Reg(Rdest_num))
		Rdest = d;
	ENDI

#endif	/* } */

#if !defined(HAS_NATIVE_sparcv9_tsub_co_rrr)	/* { */

IMPL(tsub_co_rrr)
	int64_t s1 = Rsrc1;
	int64_t s2 = Rsrc2;
	int64_t d;
	uint64_t v, c;
	uint32_t icc_v;

	d = s1 - s2;

	v = (s1 & ~s2 & ~d) | (~s1 & s2 & d);
	c = (~s1 & s2) | (d & (~s1 | s2));

	icc_v = ((v >> 31) & 1) | (((s1 | s2) >> 1) & 1) | ((s1 | s2) & 1);

	sp->v9_ccr  = V9_xcc_v((v >> 63) & 1);
	sp->v9_ccr |= V9_icc_v(icc_v);
	sp->v9_ccr |= V9_xcc_c((c >> 63) & 1);
	sp->v9_ccr |= V9_icc_c((c >> 31) & 1);
	sp->v9_ccr |= V9_xcc_n((d >> 63) & 1);
	sp->v9_ccr |= V9_icc_n((d >> 31) & 1);
	sp->v9_ccr |= V9_xcc_z(d ? 0 : 1);
	sp->v9_ccr |= V9_icc_z((d & MASK64(31,0)) ? 0 : 1);
	if (!Zero_Reg(Rdest_num))
		Rdest = d;
	ENDI

#endif	/* } */


#if !defined(HAS_NATIVE_sparcv9_tsub_co_tv_imm)	/* { */

IMPL(tsub_co_tv_imm)
	int64_t s1 = Rsrc1;
	int64_t s2 = Simm16;
	int64_t d;
	uint64_t v, c;
	uint32_t icc_v;

	d = s1 - s2;

	v = (s1 & ~s2 & ~d) | (~s1 & s2 & d);
	c = (~s1 & s2) | (d & (~s1 | s2));

	icc_v = ((v >> 31) & 1) | (((s1 | s2) >> 1) & 1) | ((s1 | s2) & 1);

	if (icc_v) {
		sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);

		v9p->post_precise_trap(sp, Sparcv9_trap_tag_overflow);
		return;
	}

	sp->v9_ccr  = V9_xcc_v((v >> 63) & 1);
	sp->v9_ccr |= V9_icc_v(icc_v);
	sp->v9_ccr |= V9_xcc_c((c >> 63) & 1);
	sp->v9_ccr |= V9_icc_c((c >> 31) & 1);
	sp->v9_ccr |= V9_xcc_n((d >> 63) & 1);
	sp->v9_ccr |= V9_icc_n((d >> 31) & 1);
	sp->v9_ccr |= V9_xcc_z(d ? 0 : 1);
	sp->v9_ccr |= V9_icc_z((d & MASK64(31,0)) ? 0 : 1);
	if (!Zero_Reg(Rdest_num))
		Rdest = d;
	ENDI

#endif	/* } */

#if !defined(HAS_NATIVE_sparcv9_tsub_co_tv_rrr)	/* { */

IMPL(tsub_co_tv_rrr)
	int64_t s1 = Rsrc1;
	int64_t s2 = Rsrc2;
	int64_t d;
	uint64_t v, c;
	uint32_t icc_v;

	d = s1 - s2;

	v = (s1 & ~s2 & ~d) | (~s1 & s2 & d);
	c = (~s1 & s2) | (d & (~s1 | s2));

	icc_v = ((v >> 31) & 1) | (((s1 | s2) >> 1) & 1) | ((s1 | s2) & 1);

	if (icc_v) {
		sparcv9_cpu_t * v9p = (sparcv9_cpu_t*)(sp->specificp);

		v9p->post_precise_trap(sp, Sparcv9_trap_tag_overflow);
		return;
	}

	sp->v9_ccr  = V9_xcc_v((v >> 63) & 1);
	sp->v9_ccr |= V9_icc_v(icc_v);
	sp->v9_ccr |= V9_xcc_c((c >> 63) & 1);
	sp->v9_ccr |= V9_icc_c((c >> 31) & 1);
	sp->v9_ccr |= V9_xcc_n((d >> 63) & 1);
	sp->v9_ccr |= V9_icc_n((d >> 31) & 1);
	sp->v9_ccr |= V9_xcc_z(d ? 0 : 1);
	sp->v9_ccr |= V9_icc_z((d & MASK64(31,0)) ? 0 : 1);
	if (!Zero_Reg(Rdest_num))
		Rdest = d;
	ENDI

#endif	/* } */


IMPL(siam)
	uint64_t mode;

	mode = Simm16;
	sp->v9_gsr = (sp->v9_gsr & ~(V9_GSR_IM_MASK|V9_GSR_IRND_MASK)) |
		((mode & 7) << V9_GSR_IRND_SHIFT);
	ENDI



IMPL( sir )
	sparcv9_cpu_t * v9p = (sparcv9_cpu_t *)(sp->specificp);

	if (V9_User == v9p->state || V9_Priv == v9p->state) {
		v9p->post_precise_trap(sp, Sparcv9_trap_illegal_instruction);
		return;
	}

	v9p->post_precise_trap(sp, Sparcv9_trap_software_initiated_reset);
		
	ENDDEF


	/*-------------------------- OLD CODE ------------------------*/




#if 0	/* { */
-- 
-- 	/**/
-- 	/* We still get crappy code from these from the Sun*/
-- 	/* compiler - eventually well re-write these entirely*/
-- 	/* as host native routines in assembler ...*/
-- 	/**/
-- 
-- 	/* BTW: cico = condition codes in+out ... not just*/
-- 	/* carry in+carry out ... note addcc sets *all* cond codes*/
-- 
-- IMPL( add_ci_imm )
-- 	Rdest = Rsrc1 + Simm16 + (Rccr & 1LL);
-- 	ENDI
-- 
-- IMPL( add_co_imm )
-- 	Rdest = il_add_co( Rsrc1, Simm16, &Rccr );
-- 	ENDI
-- 
-- IMPL( add_cico_imm )
-- 	Rdest = il_add_cico( Rsrc1, Simm16, &Rccr );
-- 	ENDI
-- 
-- IMPL( add_co_imm_rd0 )
-- 	(void)il_add_co( Rsrc1, Simm16, &Rccr );
-- 	ENDI
-- 
-- IMPL( add_cico_imm_rd0 )
-- 	(void)il_add_cico( Rsrc1, Simm16, &Rccr );
-- 	ENDI
-- 
-- IMPL( add_ci_rrr )
-- 	Rdest = Rsrc1 + Rsrc2 + (Rccr & 1LL);
-- 	ENDI
-- 
-- IMPL( add_co_rrr )
-- 	Rdest = il_add_co( Rsrc1, Rsrc2, &Rccr );
-- 	ENDI
-- 
-- IMPL( add_cico_rrr )
-- 	Rdest = il_add_cico( Rsrc1, Rsrc2, &Rccr );
-- 	ENDI
-- 
-- IMPL( add_co_rrr_rd0 )
-- 	(void)il_add_co( Rsrc1, Rsrc2, &Rccr );
-- 	ENDI
-- 
-- IMPL( add_cico_rrr_rd0 )
-- 	(void)il_add_cico( Rsrc1, Rsrc2, &Rccr );
-- 	ENDI
-- 
-- 
-- 
-- 
-- 
-- IMPL( sub_ci_imm )
-- 	Rdest = Rsrc1 - Simm16 - (Rccr & 1LL);
-- 	ENDI
-- 
-- IMPL( sub_co_imm )
-- 	Rdest = il_sub_co( Rsrc1, Simm16, &Rccr );
-- 	ENDI
-- 
-- IMPL( sub_co_imm_rd0 )
-- 	(void)il_sub_co( Rsrc1, Simm16, &Rccr );
-- 	ENDI
-- 
-- IMPL( sub_cico_imm )
-- 	Rdest = il_sub_cico( Rsrc1, Simm16, &Rccr );
-- 	ENDI
-- 
-- IMPL( sub_cico_imm_rd0 )
-- 	(void)il_sub_cico( Rsrc1, Simm16, &Rccr );
-- 	ENDI
-- 
-- IMPL( sub_ci_rrr )
-- 	Rdest = Rsrc1 - Rsrc2 - (Rccr & 1LL);
-- 	ENDI
-- 
-- IMPL( sub_co_rrr )
-- 	Rdest = il_sub_co( Rsrc1, Rsrc2, &Rccr );
-- 	ENDI
-- 
-- IMPL( sub_co_rrr_rd0 )
-- 	(void)il_sub_co( Rsrc1, Rsrc2, &Rccr );
-- 	ENDI
-- 
-- IMPL( sub_cico_rrr )
-- 	Rdest = il_sub_cico( Rsrc1, Rsrc2, &Rccr );
-- 	ENDI
-- 
-- IMPL( sub_cico_rrr_rd0 )
-- 	(void)il_sub_cico( Rsrc1, Rsrc2, &Rccr );
-- 	ENDI
-- 
-- 
-- 
-- 	/**/
-- 	/* Logic instructions*/
-- 	/**/
-- 
-- IMPL( and_imm )
-- 	Rdest = Rsrc1 & Simm16;
-- 	ENDI
-- 
-- IMPL( and_cc_imm )
-- 	Rdest = il_and_cc( Rsrc1, Simm16, &Rccr );
-- 	ENDI
-- 
-- IMPL( and_cc_imm_rd0 )
-- 	(void)il_and_cc( Rsrc1, Simm16, &Rccr );
-- 	ENDI
-- 
-- IMPL( and_rrr )
-- 	Rdest = Rsrc1 & Rsrc2;
-- 	ENDI
-- 
-- IMPL( and_cc_rrr )
-- 	Rdest = il_and_cc( Rsrc1, Rsrc2, &Rccr );
-- 	ENDI
-- 
-- IMPL( and_cc_rrr_rd0 )
-- 	(void)il_and_cc( Rsrc1, Rsrc2, &Rccr );
-- 	ENDI
-- 
-- 
-- IMPL( andn_rrr )
-- 	Rdest = Rsrc1 & ~Rsrc2;
-- 	ENDI
-- 
-- IMPL( andn_cc_rrr )
-- 	Rdest = il_andn_cc( Rsrc1, Rsrc2, &Rccr );
-- 	ENDI
-- 
-- IMPL( andn_cc_rrr_rd0 )
-- 	(void)il_andn_cc( Rsrc1, Rsrc2, &Rccr );
-- 	ENDI
-- 
-- 
-- 
-- IMPL( or_imm )
-- 	Rdest = Rsrc1 | Simm16;
-- 	ENDI
-- 
-- IMPL( or_cc_imm )
-- 	Rdest = il_or_cc( Rsrc1, Simm16, &Rccr );
-- 	ENDI
-- 
-- IMPL( or_cc_imm_rd0 )
-- 	(void)il_or_cc( Rsrc1, Simm16, &Rccr );
-- 	ENDI
-- 
-- IMPL( or_rrr )
-- 	Rdest = Rsrc1 | Rsrc2;
-- 	ENDI
-- 
-- IMPL( or_cc_rrr )
-- 	Rdest = il_or_cc( Rsrc1, Rsrc2, &Rccr );
-- 	ENDI
-- 
-- IMPL( or_cc_rrr_rd0 )
-- 	(void)il_or_cc( Rsrc1, Rsrc2, &Rccr );
-- 	ENDI
-- 
-- 
-- 
-- IMPL( orn_rrr )
-- 	Rdest = Rsrc1 | ~Rsrc2;
-- 	ENDI
-- 
-- IMPL( orn_cc_rrr )
-- 	Rdest = il_orn_cc( Rsrc1, Rsrc2, &Rccr );
-- 	ENDI
-- 
-- IMPL( orn_cc_rrr_rd0 )
-- 	(void)il_orn_cc( Rsrc1, Rsrc2, &Rccr );
-- 	ENDI
-- 
-- 
-- 
-- IMPL( xor_imm )
-- 	Rdest = Rsrc1 ^ Simm16;
-- 	ENDI
-- 
-- IMPL( xor_cc_imm )
-- 	Rdest = il_xor_cc( Rsrc1, Simm16, &Rccr );
-- 	ENDI
-- 
-- IMPL( xor_cc_imm_rd0 )
-- 	(void)il_xor_cc( Rsrc1, Simm16, &Rccr );
-- 	ENDI
-- 
-- IMPL( xor_rrr )
-- 	Rdest = Rsrc1 ^ Rsrc2;
-- 	ENDI
-- 
-- IMPL( xor_cc_rrr )
-- 	Rdest = il_xor_cc( Rsrc1, Rsrc2, &Rccr );
-- 	ENDI
-- 
-- IMPL( xor_cc_rrr_rd0 )
-- 	(void)il_xor_cc( Rsrc1, Rsrc2, &Rccr );
-- 	ENDI
-- 
-- 
-- 
-- IMPL( xnor_rrr )
-- 	Rdest = ~(Rsrc1 ^ Rsrc2);
-- 	ENDI
-- 
-- IMPL( xnor_cc_rrr )
-- 	Rdest = il_xnor_cc( Rsrc1, Rsrc2, &Rccr );
-- 	ENDI
-- 
-- IMPL( xnor_cc_rrr_rd0 )
-- 	(void)il_xnor_cc( Rsrc1, Rsrc2, &Rccr );
-- 	ENDI
-- 
-- 
-- 
-- 
-- 		/* branch with no annulled delay slot */
-- IMPL( brcond_ds )
-- 	uint64_t xpc;
-- 
-- 	cpup->cti_executed = TRUE;
-- 
-- 	if (COMPUTE_TAKEN(Rccr)) {
-- 		xpc = Rpc + SBRoffset32;
-- 	} else {
-- 		xpc = Rnpc + 4;
-- 	}
-- 	Rpc = Rnpc;
-- 	Rnpc = xpc;
-- 	ENDI
-- 
-- 
-- 		/* branch with annulled delay slot */
-- IMPL( brcond_ds_annul )
-- 	uint64_t xpc;
-- 	
-- 	cpup->cti_executed = TRUE;
-- 
-- 	if (COMPUTE_TAKEN(Rccr)) {
-- 		xpc = Rpc + SBRoffset32;
-- 	} else {
-- 		cpup->annul = TRUE;
-- 		xpc = Rnpc + 4;
-- 	}
-- 	Rpc = Rnpc;
-- 	Rnpc = xpc;
-- 	ENDI
-- 
-- 
-- 		/* branch with no annulled delay slot */
-- IMPL( br_g_le_ds )
-- 	uint64_t xpc;
-- 	uint64_t func;
-- 
-- 	func = Rccr;
-- 	func = ((func>>1) ^ (func>>3))|(func>>2);	/* get Z|(N^V) in bits 0,4 */
-- 
-- 	cpup->cti_executed = TRUE;
-- 
-- 	if (COMPUTE_TAKEN(func)) {
-- 		xpc = Rpc + SBRoffset32;
-- 	} else {
-- 		xpc = Rnpc + 4;
-- 	}
-- 	Rpc = Rnpc;
-- 	Rnpc = xpc;
-- 	ENDI
-- 
-- 
-- 		/* branch with annulled delay slot */
-- IMPL( br_g_le_ds_annul )
-- 	uint64_t xpc;
-- 	uint64_t func;
-- 
-- 	func = Rccr;
-- 	func = ((func>>1) ^ (func>>3))|(func>>2);	/* get Z|(N^V) in bits 0,4 */
-- 	
-- 	cpup->cti_executed = TRUE;
-- 
-- 	if (COMPUTE_TAKEN(func)) {
-- 		xpc = Rpc + SBRoffset32;
-- 	} else {
-- 		cpup->annul = TRUE;
-- 		xpc = Rnpc + 4;
-- 	}
-- 	Rpc = Rnpc;
-- 	Rnpc = xpc;
-- 	ENDI
-- 
-- 
-- 		/* branch with no annulled delay slot */
-- IMPL( br_ge_l_ds )
-- 	uint64_t xpc;
-- 	uint64_t func;
-- 
-- 	func = Rccr;
-- 	func = (func>>1) ^ (func>>3);	/* get (N^V) in bits 0,4 */
-- 
-- 	cpup->cti_executed = TRUE;
-- 
-- 	if (COMPUTE_TAKEN(func)) {
-- 		xpc = Rpc + SBRoffset32;
-- 	} else {
-- 		xpc = Rnpc + 4;
-- 	}
-- 	Rpc = Rnpc;
-- 	Rnpc = xpc;
-- 	ENDI
-- 
-- 
-- 		/* branch with annulled delay slot */
-- IMPL( br_ge_l_ds_annul )
-- 	uint64_t xpc;
-- 	uint64_t func;
-- 
-- 	func = Rccr;
-- 	func = (func>>1) ^ (func>>3);	/* get (N^V) in bits 0,4 */
-- 	
-- 	cpup->cti_executed = TRUE;
-- 
-- 	if (COMPUTE_TAKEN(func)) {
-- 		xpc = Rpc + SBRoffset32;
-- 	} else {
-- 		cpup->annul = TRUE;
-- 		xpc = Rnpc + 4;
-- 	}
-- 	Rpc = Rnpc;
-- 	Rnpc = xpc;
-- 	ENDI
-- 
-- 
-- 		/* branch with no annulled delay slot */
-- IMPL( br_gu_leu_ds )
-- 	uint64_t xpc;
-- 	uint64_t func;
-- 
-- 	func = Rccr;
-- 	func = (func>>2) | func;	/* get (Z|C) in bits 0,4 */
-- 
-- 	cpup->cti_executed = TRUE;
-- 
-- 	if (COMPUTE_TAKEN(func)) {
-- 		xpc = Rpc + SBRoffset32;
-- 	} else {
-- 		xpc = Rnpc + 4;
-- 	}
-- 	Rpc = Rnpc;
-- 	Rnpc = xpc;
-- 	ENDI
-- 
-- 
-- 		/* branch with annulled delay slot */
-- IMPL( br_gu_leu_ds_annul )
-- 	uint64_t xpc;
-- 	uint64_t func;
-- 
-- 	func = Rccr;
-- 	func = (func>>2) | func;	/* get (Z|C) in bits 0,4 */
-- 	
-- 	cpup->cti_executed = TRUE;
-- 
-- 	if (COMPUTE_TAKEN(func)) {
-- 		xpc = Rpc + SBRoffset32;
-- 	} else {
-- 		cpup->annul = TRUE;
-- 		xpc = Rnpc + 4;
-- 	}
-- 	Rpc = Rnpc;
-- 	Rnpc = xpc;
-- 	ENDI
-- 
-- 
-- 
-- IMPL( bralways_ds )
-- 	uint64_t xpc;
-- 	cpup->cti_executed = TRUE;
-- 
-- 	xpc = Rpc + SBRoffset32;
-- 	Rpc = Rnpc;
-- 	Rnpc = xpc;
-- 	ENDI
-- 
-- 
-- IMPL( bralways_ds_annul )
-- 	uint64_t xpc;
-- 	cpup->cti_executed = TRUE;
-- 
-- 	cpup->annul = TRUE;
-- 	xpc = Rpc + SBRoffset32;
-- 	Rpc = Rnpc;
-- 	Rnpc = xpc;
-- 	ENDI
-- 
-- 
-- 
-- IMPL( brnever_ds_annul )
-- 	cpup->cti_executed = TRUE;
-- 
-- 	cpup->annul = TRUE;
-- 	Rpc = Rnpc;
-- 	Rnpc += 4;
-- 	ENDI
-- 
-- 
#endif /* } */

